公开(公告)号：DE69316810T2

公开(公告)日：1998-08-13

申请号：DE69316810

申请日：1993-07-16

Applicant: IBM

Inventor： BURGHARTZ JOACHIM N ,  MEYERSON BERNARD ,  SUN YAUN-CHEN

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/772

Abstract: A dual gate thin film or SOI MOSFET device having a sufficiently thin body thickness with one or more semiconductor channel layer(s) sandwiched by semiconductor layers having a different energy band structure to automatically confine carriers to the channel layer(s) without the need for channel grading or modulation doping. Preferred embodiments employ strained layer epitaxy having Si/SiGe/Si or SiGe/Si/SiGe semiconductor layers. The SiGe Thin Film Transistor (100) has a SiGe channel (102), sandwiched between two thin Si layers (104, 106). The top Si layer (104) is also called a top channel or first spacer layer, and the bottom Si layer (106) is also called a substrate channel or second spacer layer. A pair of top and bottom gate electrodes (108, 110) are used to modulate carriers in the channel and thereby turn the transistor on and off in a known fashion. High quality silicon dioxide (SiO2) gate insulators (112, 114) can be deposited or thermally grown thereon. High conductivity source and drain regions (116, 118), are also provided. Connection to, and biasing of, the gates, and the source/drain regions are performed in a conventional manner.

公开(公告)号：CA1311859C

公开(公告)日：1992-12-22

申请号：CA601601

申请日：1989-06-02

Applicant: IBM

Inventor： BURGHARTZ JOACHIM N ,  GINSBERG BARRY J ,  MADER SIEGFRIED R

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L21/20 ,  H01L29/72

Abstract: BIPOLAR TRANSISTOR HAVING SELF-ALIGNED EMITTER-BASE AND METHOD OF FORMING SAME USING SELECTIVE AND NON-SELECTIVE EPITAXY Selective and non-selective epitaxial growth is utilized to form a bipolar transistor having self-aligned emitter and base regions. A substrate of semiconductor material of a first conductivity type is provided and a first layer of semiconductor material of a second conductivity type is non-selectively epitaxially grown on the substrate. An insulating element is formed on a portion of the first layer of semiconductor material and a second layer of semiconductor material of the second conductivity type is selectively epitaxially grown on the first layer such that a portion of the second layer laterally overgrows onto an upper surface of the insulating element. The lateral overgrowth forms an aperture in the second layer to expose a region of the upper surface of insulating element, A layer of insulating material is formed on the accond layer to isolate the second layer of semiconductor material from a subsequent deposition of conductive material. The portion of the insulating layer formed within the aperture narrows the aperture and the exposed region of the element. The exposed region of the element is removed to expose a portion of the first layer and an emitter region of the first conductivity type is formed in the first layer through the aperture. Y0988-038

公开(公告)号：DE69316810D1

公开(公告)日：1998-03-12

申请号：DE69316810

申请日：1993-07-16

Applicant: IBM

Inventor： BURGHARTZ JOACHIM N ,  MEYERSON BERNARD ,  SUN YAUN-CHEN

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/772

Abstract: A dual gate thin film or SOI MOSFET device having a sufficiently thin body thickness with one or more semiconductor channel layer(s) sandwiched by semiconductor layers having a different energy band structure to automatically confine carriers to the channel layer(s) without the need for channel grading or modulation doping. Preferred embodiments employ strained layer epitaxy having Si/SiGe/Si or SiGe/Si/SiGe semiconductor layers. The SiGe Thin Film Transistor (100) has a SiGe channel (102), sandwiched between two thin Si layers (104, 106). The top Si layer (104) is also called a top channel or first spacer layer, and the bottom Si layer (106) is also called a substrate channel or second spacer layer. A pair of top and bottom gate electrodes (108, 110) are used to modulate carriers in the channel and thereby turn the transistor on and off in a known fashion. High quality silicon dioxide (SiO2) gate insulators (112, 114) can be deposited or thermally grown thereon. High conductivity source and drain regions (116, 118), are also provided. Connection to, and biasing of, the gates, and the source/drain regions are performed in a conventional manner.