公开(公告)号：GB2318936A

公开(公告)日：1998-05-06

申请号：GB9720705

申请日：1997-09-30

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT P ,  MUHICH JOHN S

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/081 ,  H03L7/18 ,  H03L7/06 ,  G06F1/08

Abstract: A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit which includes a device which generates a reference frequency 26, an acoustic wave oscillator 18 having an oscillation frequency slightly faster than the reference frequency 26 and a circuit configuration coupled to the acoustic wave oscillator which generates frequency signals in response to an output of the acoustic wave oscillator. The frequency signals carry negligible jitter. The circuit configuration includes a quadrature rotator 12 for controlling clock phase, a clock distributor 14 for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider 24 which provides a feedback clock signal phase aligned with the reference frequency, a phase detector 22 for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter 20 responsive to the phase detector.

公开(公告)号：CA2254637A1

公开(公告)日：1999-07-07

申请号：CA2254637

申请日：1998-11-26

Applicant: IBM

Inventor： DREPS DANIEL M ,  MUHICH JOHN S ,  MASLEID ROBERT P

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/08 ,  G06F1/12

Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.

公开(公告)号：CA2254637C

公开(公告)日：2003-07-22

申请号：CA2254637

申请日：1998-11-26

Applicant: IBM

Inventor： MASLEID ROBERT P ,  MUHICH JOHN S ,  DREPS DANIEL M

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/08 ,  G06F1/12

Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.

公开(公告)号：GB2318936B

公开(公告)日：2001-01-17

申请号：GB9720705

申请日：1997-09-30

Applicant: IBM

Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT P ,  MUHICH JOHN S

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/081 ,  H03L7/18 ,  H03L7/06 ,  G06F1/08

Abstract: A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit. The clock generation apparatus includes a device which generates a reference frequency, an acoustic wave oscillator having an oscillation frequency slightly faster than the reference frequency and a circuit configuration coupled to the acoustic wave oscillator which generates frequency bearing signals in response to an output of the acoustic wave oscillator. The frequency bearing signals carry negligible jitter. The circuit configuration includes a quadrature rotator for controlling clock phase, a clock distributor for efficiently dispersing clock signals to the microprocessor integrated circuit, a bus divider which provides a feedback clock signal phase aligned with the reference frequency, a phase detector for detecting the phase difference of a bus clock signal and the feedback clock signal, and a digital filter responsive to the phase detector.

公开(公告)号：CA2254651A1

公开(公告)日：1999-07-07

申请号：CA2254651

申请日：1998-11-26

Applicant: IBM

Inventor： MUHICH JOHN S ,  MASLEID ROBERT P ,  DREPS DANIEL M

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/00 ,  H03L7/07 ,  H04L7/02 ,  G06F1/12 ,  H03L7/08

Abstract: A method and apparatus are provided for generating synchronized clock signals. According to the method and apparatus, first and second pluralities of signals are generated, having time-varying phase differences with respect to a reference clock. The first clock is supplied by a succession of signals from among the first plurality of signals, in which one of the signals succeeds another responsive to a first phase difference. The second clock is supplied by a second succession of signals from among the second plurality of signals. One signal in the second succession of signals succeeds another responsive to a second phase difference. The succession among the first plurality of signals is also responsive to the second phase difference.