公开(公告)号：CA2254637A1

公开(公告)日：1999-07-07

申请号：CA2254637

申请日：1998-11-26

Applicant: IBM

Inventor： DREPS DANIEL M ,  MUHICH JOHN S ,  MASLEID ROBERT P

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/08 ,  G06F1/12

Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.

公开(公告)号：GB2513529A

公开(公告)日：2014-11-05

申请号：GB201220534

申请日：2012-11-15

Applicant: IBM

Inventor： HARRER HUBERT ,  DREPS DANIEL M ,  FERRAIOLO FRANK D ,  WEBEL TOBIAS ,  WEISS ULRICH ,  TONG CHING-LUNG L ,  MAK PAK-KIN

IPC: G06F1/12 ,  G06F1/08 ,  G06F13/40

Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency, the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.

公开(公告)号：CA2254637C

公开(公告)日：2003-07-22

申请号：CA2254637

申请日：1998-11-26

Applicant: IBM

Inventor： MASLEID ROBERT P ,  MUHICH JOHN S ,  DREPS DANIEL M

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/08 ,  G06F1/12

Abstract: Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.

公开(公告)号：CA2254651A1

公开(公告)日：1999-07-07

申请号：CA2254651

申请日：1998-11-26

Applicant: IBM

Inventor： MUHICH JOHN S ,  MASLEID ROBERT P ,  DREPS DANIEL M

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/00 ,  H03L7/07 ,  H04L7/02 ,  G06F1/12 ,  H03L7/08

Abstract: A method and apparatus are provided for generating synchronized clock signals. According to the method and apparatus, first and second pluralities of signals are generated, having time-varying phase differences with respect to a reference clock. The first clock is supplied by a succession of signals from among the first plurality of signals, in which one of the signals succeeds another responsive to a first phase difference. The second clock is supplied by a second succession of signals from among the second plurality of signals. One signal in the second succession of signals succeeds another responsive to a second phase difference. The succession among the first plurality of signals is also responsive to the second phase difference.