公开(公告)号：EP1850342A4

公开(公告)日：2009-04-08

申请号：EP05820131

申请日：2005-12-21

Applicant: IBM

Inventor： MATSUO HISATO ,  FUKUDA JUNICHI

IPC: G11B20/18 ,  G06F13/00 ,  G11B20/10

CPC classification number: G11B20/1803 ,  G11B20/1833 ,  G11B2020/10629 ,  G11B2020/1823 ,  G11B2020/1853 ,  G11B2220/90

Abstract: An information recording device for transferring error-corrected subunits only partially, when the corrected data is returned from error correcting means to an external buffer, and a data-flow control method for the device. The information recording device records the data, in which a correction code is added to user data of plural bytes transferred from a host device, in a recording medium, corrects an error of the data read from the recording medium, with the correction code, and transfers the user data to the host device. The information recording device comprises an external buffer for temporarily storing the data read from the recording medium, error correcting means for correcting the error of the data transferred from the external buffer thereby to create the correction data, and for dividing the corrected data into a plurality of subunits thereby to attach a transfer flag to the subunits containing the corrected data, and data-flow means for transferring only the subunit having the transfer flag attached thereto, to the external buffer when the corrected data is sent from the error correcting means to the external buffer, and for rewriting only the portion of the subunits of the data stored in the external buffer.

公开(公告)号：JP2011113119A

公开(公告)日：2011-06-09

申请号：JP2009266286

申请日：2009-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MATSUO HISATO ,  TANAKA KEISUKE ,  DEMURA MASAYUKI

IPC: G06F12/00 ,  G06F13/362

CPC classification number: G06F13/161 ,  G06F13/1673 ,  Y02D10/14

Abstract: PROBLEM TO BE SOLVED: To provide a memory access device for sharing a buffer for data flows of an information device and a main memory for a processor. SOLUTION: An arbiter unit assigns access requests to the memory from a plurality of functional blocks sequentially by a round-robin method with a predetermined transfer length. (a) Data transfer from a functional block is split into partial transfers by a predetermined transfer length, and a plurality of partial transfers are performed according to a band for data transfer in one round-robin cycle. (b) The plurality of partial transfers have different priorities, and the priorities are programmably set up so that the required band of data transfer from all functional blocks may be satisfied by alternate transfer of the partial transfers from different functional blocks. (c) An access from the processor is executed so that the number of accesses from the processor to the memory may exert less effect on bands for data flow transfers with top priority and with a predetermined transfer length (CPU transfer length) in predetermined intervals between the transfer blocks. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于共享用于处理器的信息设备和主存储器的数据流的缓冲器的存储器访问设备。 解决方案：仲裁器单元通过具有预定传送长度的循环方法顺序地从多个功能块向存储器分配访问请求。 （a）从功能块的数据传送被分割成预定传送长度的部分传送，并且根据用于一轮循环的数据传送的频带执行多个部分传送。 （b）多个部分传送具有不同的优先级，并且可编程地设置优先级，使得可以通过从不同功能块的部分传输的交替传送来满足来自所有功能块的所需数据传送频带。 （c）执行来自处理器的访问，使得从处理器到存储器的访问次数可以对具有最高优先级的数据流传输的频带施加较小的影响，并且以预定的传送长度（CPU传送长度）以 传输块。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2011124630A3

公开(公告)日：2011-12-22

申请号：PCT/EP2011055392

申请日：2011-04-07

Applicant: IBM ,  CIDECIYAN ROY DARON ,  MATSUO HISATO ,  MITTELHOLZER THOMAS ,  OHTANI KENJI ,  SEGER PAUL ,  TANAKA KEISUKE

Inventor： CIDECIYAN ROY DARON ,  MATSUO HISATO ,  MITTELHOLZER THOMAS ,  OHTANI KENJI ,  SEGER PAUL ,  TANAKA KEISUKE

IPC: G11B20/18

CPC classification number: G11B20/18 ,  G11B2020/184 ,  G11B2020/1853 ,  G11B2220/90

Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.

Abstract translation: 在磁带驱动器中集成数据和标题保护的方法包括接收组织成行和列的数据阵列。 数组被扩展为包含数组中每行数据的一个或多个头。 该方法为阵列中的数据提供纠错码（ECC）保护的两个维度，并为阵列中的头部提供单维度ECC保护。 本文还公开了相应的装置。

公开(公告)号：JP2001298875A

公开(公告)日：2001-10-26

申请号：JP2000116434

申请日：2000-04-18

Applicant: IBM

Inventor： TSUJIKADO SEIJI ,  KUBO TAKUYA ,  MATSUO HISATO

IPC: G06F1/28 ,  G06F1/26 ,  G06F1/30 ,  H02J9/00 ,  H02J9/06

Abstract: PROBLEM TO BE SOLVED: To enhance the life of a battery for backing up AC input. SOLUTION: An ON signal (SW-ON) for commanding power on is supplied to a terminal 52, the output (Q) of flip flop circuits FF64 and FF66 comes to high level(H), a signal (AC-ON/OFF) is outputted to PC, and system starting processing is started with the power supply by commercial power source. An OFF signal (SW-OFF) for commanding power OFF is supplied to a terminal 54, and the output of FF64 comes to low level(L), but the output of the FF circuit 66 keeps H until a shut down signal (shutdown COMP) is inputted from PC, so it is never switched over to the power supply of battery. In case of power failure, the signal (line-on) becomes L, so the output of an AND circuit 70 becomes H, and it is switched over to the power supply of battery until the power break treatment is finished.

公开(公告)号：JP2008217860A

公开(公告)日：2008-09-18

申请号：JP2007050772

申请日：2007-02-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MATSUO HISATO

IPC: G11B20/10 ,  G06F3/06 ,  G11B20/18

CPC classification number: G06F3/0656 ,  G06F3/0613 ,  G06F3/0682

Abstract: PROBLEM TO BE SOLVED: To provide a technique capable of managing the processing situation of each block of hardware using a reduced number of registers. SOLUTION: A processing system comprises a buffer, a plurality of processing parts, a plurality of first tables, and a management part. The buffer consists of a plurality of segments respectively storing data inputted to the processing system in the order of input and by units of processing. The processing parts execute a series of processings to the data in a predetermined order. The plurality of first tables respectively correspond to the processing parts and respectively store leading head information indicating the leading head segment out of the segments in which data processings by corresponding processing parts are finished and whose addresses are continuous, tail end information indicating the tail end segment out of the same segments, and existence information indicating the presence/absence of the segments in which data processings by corresponding processing parts are finished. The management part manages data transfer between the buffer and the processing parts so that a series of processings are executed in the predetermined order on the basis of the processing situation of the series of processings held by the first tables. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够使用减少数量的寄存器来管理每个硬件块的处理情况的技术。 解决方案：处理系统包括缓冲器，多个处理部件，多个第一表格和管理部件。 该缓冲器包括多个段，分别以输入顺序和处理单元存储输入到处理系统的数据。 处理部件以预定顺序对数据执行一系列处理。 多个第一表分别对应于处理部分，并且分别存储指示由对应处理部分完成的数据处理并且其地址是连续的段之中的前导头段的前导头信息，指示尾端段的尾端信息 以及表示相应处理部分的数据处理完成的段的存在/不存在的存在信息。 管理部件管理缓冲器和处理部件之间的数据传送，从而基于由第一表保存的一系列处理的处理情况，以预定顺序执行一系列处理。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：GB2512548A

公开(公告)日：2014-10-01

申请号：GB201412792

申请日：2012-12-10

Applicant: IBM

Inventor： SCHAFFER SCOTT JEFFREY ,  NAGAHARA RIKA ,  MATSUO HISATO

IPC: G06F15/167 ,  G06F9/54

Abstract: A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

公开(公告)号：GB2490831A

公开(公告)日：2012-11-14

申请号：GB201214869

申请日：2011-04-07

Applicant: IBM

Inventor： CIDECIYAN ROY ,  MATSUO HISATO ,  MITTELHOLZER THOMAS ,  OHTANI KENJI ,  SEGER PAUL ,  TANAKA KEISUKE

IPC: G11B20/18

Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.

公开(公告)号：DE112011103916B4

公开(公告)日：2021-11-25

申请号：DE112011103916

申请日：2011-10-06

Applicant: IBM

Inventor： MATSUO HISATO ,  NAGAHARA RIKA ,  OHTANI KENJI

IPC: G06F12/06 ,  G06F3/00 ,  G06F13/16

Abstract: Speicherzugriffseinheit für gemeinsame Nutzung eines Speichers (43) für Hauptspeicher (452) mehrerer CPUs (49) und einen Datenpuffer (451) anderer Funktionsblöcke, wobei die Einheit aufweist:mehrere CPUs (49) nutzen einen Speicher (43) als Hauptspeicher (452);andere Funktionsblöcke nutzen den Speicher (43) als diesen Datenpuffer (451);eine mit einem Bus (48) für die CPUs (49) verbundene CPU-Schnittstellenschaltung (52), um Speicherzugriffsanfragen von den mehreren CPUs zu steuern; undeine mit der CPU-Schnittstellenschaltung (52) verbundene Speichersteuereinheit (46), um Speicherzugriffs(CPU-Zugriffs- und Funktionsblockzugriffs)-Anfragen von den CPUs (49) und den Funktionsblöcken zu arbitrieren;wobei die CPU-Schnittstellenschaltung (52)Speicherzugriffsanfragen von den mehreren CPUs (49) zurückhält,eine Adresse, einen Datenübertragungsmodus und einen Datenumfang jedes CPU-Zugriffs empfängt und speichert,die Speichersteuereinheit (46) über die Zugriffsanfragen benachrichtigt,bei Empfangen eines Zugelassen-Signals für die Zugriffsanfragen die Informationen als Reaktion auf das Zugelassen-Signal an die Speichersteuereinheit (46) sendet, undbei Nicht-Empfangen des Zugelassen-Signals für die Zugriffsanfragen die wartenden Zugriffsanfragen von den mehreren CPUs (49) zurückhält, unddie Speichersteuereinheit (46)die Zugriffsanfragesignale empfängt, eine CPU (49) angibt, deren Zugriffsanfragen von der Zugriffsarbitrierung zugelassen wurden, und das Zugelassen-Signal an die CPU-Schnittstellenschaltung (52) sendet und die mehreren CPU-Zugriffsanfragen in einem einzigen Buszyklus ausführt, undbei Empfangen mehrerer CPU-Zugriffsanfragen im Falle, dass gerade eine Datenflussübertragung des anderen Funktionsblocks durchgeführt wird, die mehreren CPU-Zugriffsanfragen zurückhält und die mehreren CPU-Anfragen nach Abschluss der Datenflussübertragung vom Funktionsblock in einem einzigen Übertragungszyklus durchführt.

公开(公告)号：GB2500529A

公开(公告)日：2013-09-25

申请号：GB201311026

申请日：2011-10-06

Applicant: IBM

Inventor： MATSUO HISATO ,  NAGAHARA RIKA ,  OHTANI KENJI

IPC: G06F13/16 ,  G06F13/366

Abstract: Provided is a memory access device for a shared memory mechanism of main memory for a plurality of CPUs. The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.

公开(公告)号：DE112011100199T5

公开(公告)日：2012-11-29

申请号：DE112011100199

申请日：2011-04-07

Applicant: IBM

Inventor： MATSUO HISATO ,  OHTANI KENJI ,  SEGER PAUL ,  CIDECIYAN ROY DARON ,  MITTELHOLZER THOMAS ,  TANAKA KEISUKE

IPC: G11B20/18

Abstract: Ein Verfahren zum Integrieren von Daten- und Vorsatzschutz bei Bandlaufwerken beinhaltet das Empfangen einer in Zeilen und Spalten gegliederten Datenanordnung. Die Anordnung wird so erweitert, dass sie einen oder mehrere Vorsätze für jede Datenzeile in der Anordnung beinhaltet. Das Verfahren stellt zwei Dimensionen von Fehlerkorrekturcode(ECC)-Schutz für die Daten in der Anordnung und eine einzige Dimension von ECC-Schutz für die Vorsätze in der Anordnung bereit. Eine entsprechende Vorrichtung wird hierin ebenfalls offenbart.