公开(公告)号：CA1104264A

公开(公告)日：1981-06-30

申请号：CA295779

申请日：1978-01-26

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  HOOD ROBERT A ,  MAYES GARY W

Abstract: DATA PROCESSING SYSTEM WITH IMPROVED BIT FIELD HANDLING Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruction set.

公开(公告)号：FR2357959A1

公开(公告)日：1978-02-03

申请号：FR7707756

申请日：1977-03-11

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  MAYES GARY W ,  MCDERMOTT THOMAS S ,  WISE LARRY P

IPC: G06F9/40 ,  G06F9/42 ,  G06F9/18

Abstract: A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.

公开(公告)号：FR2376460A1

公开(公告)日：1978-07-28

申请号：FR7735664

申请日：1977-11-18

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  HOOD ROBERT A ,  MAYES GARY W

IPC: G06F9/305 ,  G06F9/34 ,  G06F12/04 ,  G06F9/06 ,  G06F7/38

Abstract: A method of accessing variable-length bit fields in the memory of an electronic data processing system irrespective of the relationship between the boundaries of addressable elements within said memory and the start and end of the bit fields comprising the operations of: setting the initial values of a base register within said system to contain a representation of a base address of an addressable element; setting the initial values of a shift register within said system to contain a representation of the offset in said memory of the beginning of a particular bit field from said base address; combining the contents of said base and offset registers in such a way as to provide a representation of the position in said memory of the first bit of said particular bit field; create a single instruction that contains a representation of the length of said particular bit field. (Machine-translation by Google Translate, not legally binding)

公开(公告)号：CA1089105A

公开(公告)日：1980-11-04

申请号：CA281826

申请日：1977-06-30

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  MAYES GARY W ,  MCDERMOTT THOMAS S ,  WISE LARRY E

IPC: G06F9/18

Abstract: DATA PROCESSING SYSTEM FEATURING SUBROUTINE LINKAGE OPERATIONS USING HARDWARE CONTROLLED STACKS A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.

公开(公告)号：AU2475477A

公开(公告)日：1978-11-09

申请号：AU2475477

申请日：1977-05-02

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  MAYES GARY W ,  MCDERMOTT THOMAS S ,  WISE LARRY E

IPC: G06F9/40 ,  G06F9/42 ,  G06F9/16

Abstract: A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.