公开(公告)号：CA1092716A

公开(公告)日：1980-12-30

申请号：CA275572

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/14 ,  G06F15/16 ,  G06F15/177 ,  G06F21/24 ,  G06F13/00

Abstract: KEY REGISTER CONTROLLED ACCESSING SYSTEM Active address key (AAK) select circuits relate plural key register sections to respective machine-identifiable access types. On each received storage access request, the AAK select circuits outgate an AAK from the key register section corresponding to the machine-identi-fied type for the storage access request. One or more key register sections are provided in an address key register (AKR) in a processor. Other key register sections are provided with I/O subchannels which connect to the channels of a processor. Priority circuits control the sequence of storage access requests received by the AAK select circuits. Different machine-identifiable access types which are sensed in the machine include the instruction fetch, source operand fetch, sink operand store/fetch, and I/O data store/fetch.

公开(公告)号：CA1078068A

公开(公告)日：1980-05-20

申请号：CA275571

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F9/00

Abstract: ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEM Instruction operated controls for loading or storing key values into or from one or more key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register(GPR). Both the load or store controls can be operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

公开(公告)号：CA1104264A

公开(公告)日：1981-06-30

申请号：CA295779

申请日：1978-01-26

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  HOOD ROBERT A ,  MAYES GARY W

Abstract: DATA PROCESSING SYSTEM WITH IMPROVED BIT FIELD HANDLING Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruction set.

公开(公告)号：CA1075823A

公开(公告)日：1980-04-15

申请号：CA275543

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  MCDERMOTT THOMAS S ,  WISE LARRY E

IPC: G06F12/06 ,  G06F12/14 ,  G06F13/00

Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR). The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory. However, if the APM bit is off while the supervisor bit is on, alI instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor. But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute. BC9-76-011

公开(公告)号：FR2349919A1

公开(公告)日：1977-11-25

申请号：FR7706854

申请日：1977-03-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  MCDERMOTT THOMAS S ,  WISE LARRY E

IPC: G06F12/06 ,  G06F12/14 ,  G11C8/00 ,  G06F9/20

Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).

公开(公告)号：FR2357982A1

公开(公告)日：1978-02-03

申请号：FR7706859

申请日：1977-03-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  HOOD ROBERT A

IPC: G06F12/06 ,  G06F12/14 ,  G11C8/00 ,  G06F9/20

Abstract: The disclosure describes equate operand spaces (EOS) control over the addressabilities accessed by means of different address keys in an address key register (AKR) in a processor. Executing instructions, and their source and sink type operands may have different address keys in the AKR, and therefore different addressabilities. When enabled, the EOS control forces each source operand fetch to occur within the sink operand addressability specified in the AKR, even though the AKR explicitly contains a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKR stores whether the EOS state is enabled or disabled in the processor.

公开(公告)号：FR2357981A1

公开(公告)日：1978-02-03

申请号：FR7706852

申请日：1977-03-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G11C8/00 ,  G06F9/20

Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

公开(公告)号：AU2475177A

公开(公告)日：1978-02-02

申请号：AU2475177

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  HOOD ROBERT A

IPC: G06F12/06 ,  G06F12/14 ,  G06F13/06

Abstract: The disclosure describes equate operand spaces (EOS) control over the addressabilities accessed by means of different address keys in an address key register (AKR) in a processor. Executing instructions, and their source and sink type operands may have different address keys in the AKR, and therefore different addressabilities. When enabled, the EOS control forces each source operand fetch to occur within the sink operand addressability specified in the AKR, even though the AKR explicitly contains a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKR stores whether the EOS state is enabled or disabled in the processor.

公开(公告)号：CA1087754A

公开(公告)日：1980-10-14

申请号：CA275598

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  HOOD ROBERT A

IPC: G06F12/06 ,  G06F12/14 ,  G06F9/20

Abstract: EQUATE OPERAND ADDRESS SPACE CONTROL SYSTEM Equate operand spaces (EOS) control over the addressabilities provided by different address keys in an address key register (AKR) in a processor. When enabled, the EOS control forces each source operand access to occur within the sink operand addressability specified in the AKR, even though the AKR explicitly specifies a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKR stores whether the EOS state is enabled in the processor. The EOS field is connected to active address key (AAK) select circuits. When the EOS state is enabled, it outgates from the AKR the sink operand address key as the AAK in response to a source operand request. The source operand address key in the AKR is not disturbed by EOS enablement or disablement. Upon disabling the EOS state, the AAK select circuits resume any separate addressabilities available in the AKR for the source and sink operands.

公开(公告)号：CA1081859A

公开(公告)日：1980-07-15

申请号：CA275573

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  GRAYBIEL LYNN A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F12/14 ,  G06F12/02 ,  G06F9/20

Abstract: KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM Translates each active address key (AAK) into a respective addressability in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Address keys are contained in plural key register sections, and AAK select circuits outgate to the translator each M K from a key register section corresponding to the access type for each storage access request currently received from a processor or I/O channel. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block. Each stack can translate a contiguous set of logical program addresses into physical addresses. Any stack can support all logical addresses apparent to a program, although the machine can cause a single program to access plural addressabilities due to the machine assignment of address keys. For each storage access request for a logical program address, a stack is addressed by the AAK to determine an addressability. Then a register in the stack is addressed by high-order bits in the logical program address. The addressed register outputs the translated block address. The main memory can have any physical size in relation to the number of stacks, and to the number of segmentation registers in each stack.