公开(公告)号：US3905025A

公开(公告)日：1975-09-09

申请号：US46133774

申请日：1974-04-16

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  LOFFREDO JOHN M ,  WISE LARRY E ,  RICKARD PATRICK L

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F3/00

CPC classification number: G06F9/4812 ,  G06F9/462 ,  G06F9/4818 ,  G06F13/26

Abstract: This data acquisition and control system includes many features for enhancing real time response to external or internal conditions. One feature relates to the use of multiple processor control circuits which can be switched between active and inactive status for controlling the performance of processor operations as a function of the level of priority of received interrupt service requests. Another feature pertains to I/O devices attached to the processor. These I/O devices include means for retaining data dynamically allocable by the processor program for specifying assigned interrupt levels and/or for identifying the requisite servicing subroutine in the processor to permit rapid response when an interrupt service is granted. The devices monitor their own status and provide a summary bit to the processor identifying whether or not a status data interchange is required. Multiple masking allows the processor to select between masking all interrupts, interrupts from any source on one or more interrupt priority levels, interrupts from a particular device or devices, or any combination of these.

Abstract translation: 该数据采集和控制系统包括许多功能，用于增强对外部或内部条件的实时响应。 一个特征涉及使用多个处理器控制电路，其可以在主动和非活动状态之间进行切换，以根据接收的中断服务请求的优先级来控制处理器操作的性能。 另一个特征涉及连接到处理器的I / O设备。 这些I / O设备包括用于保留由处理器程序动态分配的用于指定分配的中断级别的数据和/或用于在处理器中识别必需的服务子例程以允许在给予中断服务时的快速响应的装置。 设备监控自己的状态，并向处理器提供摘要位，识别是否需要状态数据交换。 多重屏蔽允许处理器在一个或多个中断优先级别的屏蔽所有中断，任何源的中断，特定设备或设备的中断或这些的任何组合之间进行选择。

公开(公告)号：CA1092716A

公开(公告)日：1980-12-30

申请号：CA275572

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/06 ,  G06F12/14 ,  G06F15/16 ,  G06F15/177 ,  G06F21/24 ,  G06F13/00

Abstract: KEY REGISTER CONTROLLED ACCESSING SYSTEM Active address key (AAK) select circuits relate plural key register sections to respective machine-identifiable access types. On each received storage access request, the AAK select circuits outgate an AAK from the key register section corresponding to the machine-identi-fied type for the storage access request. One or more key register sections are provided in an address key register (AKR) in a processor. Other key register sections are provided with I/O subchannels which connect to the channels of a processor. Priority circuits control the sequence of storage access requests received by the AAK select circuits. Different machine-identifiable access types which are sensed in the machine include the instruction fetch, source operand fetch, sink operand store/fetch, and I/O data store/fetch.

公开(公告)号：CA1078068A

公开(公告)日：1980-05-20

申请号：CA275571

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F9/00

Abstract: ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEM Instruction operated controls for loading or storing key values into or from one or more key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register(GPR). Both the load or store controls can be operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

公开(公告)号：CA1104264A

公开(公告)日：1981-06-30

申请号：CA295779

申请日：1978-01-26

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  HOOD ROBERT A ,  MAYES GARY W

Abstract: DATA PROCESSING SYSTEM WITH IMPROVED BIT FIELD HANDLING Hardware facilities are described whereby the handling of data represented by variable length fields of bits may be made faster, use less storage and be less prone to errors in programming. The bit fields are handled independently of the natural storage addressing elements and boundaries. Data may be packed into main storage with the highest efficiency, and manipulated with a fast and efficient hardware instruction set.

公开(公告)号：CA1075823A

公开(公告)日：1980-04-15

申请号：CA275543

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  MCDERMOTT THOMAS S ,  WISE LARRY E

IPC: G06F12/06 ,  G06F12/14 ,  G06F13/00

Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR). The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory. However, if the APM bit is off while the supervisor bit is on, alI instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor. But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute. BC9-76-011

公开(公告)号：FR2349919A1

公开(公告)日：1977-11-25

申请号：FR7706854

申请日：1977-03-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  MCDERMOTT THOMAS S ,  WISE LARRY E

IPC: G06F12/06 ,  G06F12/14 ,  G11C8/00 ,  G06F9/20

Abstract: System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).

公开(公告)号：CA1014666A

公开(公告)日：1977-07-26

申请号：CA197463

申请日：1974-04-11

Applicant: IBM

Inventor： BROWN WENDELL W ,  DAVIS MICHAEL I ,  PIPITONE RALPH M

IPC: G06F9/48 ,  G06F9/46

Abstract: A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.

公开(公告)号：CA1111924A

公开(公告)日：1981-11-03

申请号：CA277288

申请日：1977-04-29

Applicant: IBM

Inventor： BOUKNECHT MAX A ,  DAVIS MICHAEL I ,  VERGARI LOUIS P

IPC: G06F3/00 ,  G06F13/26 ,  G06F13/34 ,  G06F3/04 ,  G06F13/00

Abstract: INPUT/OUTPUT INTERFACE LOGIC FOR CONCURRENT OPERATIONS A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

公开(公告)号：FR2357981A1

公开(公告)日：1978-02-03

申请号：FR7706852

申请日：1977-03-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G11C8/00 ,  G06F9/20

Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

公开(公告)号：FR2357959A1

公开(公告)日：1978-02-03

申请号：FR7707756

申请日：1977-03-11

Applicant: IBM

Inventor： DAVIS MICHAEL I ,  MAYES GARY W ,  MCDERMOTT THOMAS S ,  WISE LARRY P

IPC: G06F9/40 ,  G06F9/42 ,  G06F9/18

Abstract: A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.