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    1.
    发明专利
    未知

    公开(公告)号：DE2332603A1

    公开(公告)日：1974-02-21

    申请号：DE2332603

    申请日：1973-06-27

    Applicant: IBM

    Inventor： BURK JOHN LESLIE ,  MCGILVRAY BRUCE LLOYD ,  HOGAN JUN SPURGEON GRAVES ,  LARSON RUSSELL HALL

    IPC: G06F12/08 ,  G06F12/10 ,  G06F13/06

    Abstract: This specification describes a virtual memory system comprising a main storage and a smaller high speed buffer. Both main storage and the buffer are real-address oriented. Current virtual-to-real address translations are retained in a Translation Look Aside Table (TLAT) and real addresses of data stored in the buffer are maintained in a buffer directory. The CPU-provided virtual address causes access to the TLAT and to the buffer directory. The virtual address stored in the word accessed from the TLAT is compared to the virtual address from the CPU and the real addresses accessed from the TLAT and the buffer directory are compared to each other. If both comparisons are equal, the data is accessed from the buffer.

    STORE-IN-CACHE MULTIPROCESSOR SYSTEM WITH CHECKPOINT FEATURE
    5.
    发明专利
    STORE-IN-CACHE MULTIPROCESSOR SYSTEM WITH CHECKPOINT FEATURE 未知

    公开(公告)号：DE3278890D1

    公开(公告)日：1988-09-22

    申请号：DE3278890

    申请日：1982-02-05

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  GERARDI JOHN ANTHONY ,  MCGILVRAY BRUCE LLOYD

    IPC: G06F12/08 ,  G06F12/12 ,  G06F15/16 ,  G06F15/177

    Abstract: A lock array (10) is provided with bit positions corresponding to each line entry in an associated cache directory (PD). When a lock bit (L) is on, it inhibits the castout, replacement, or invalidation of the associated cache line. Lock array controls (12) operate with a slot replacement selection circuit (42; which may be conventional) to eliminate each locked slot from being a replacement candidate in its congruence class in a set-associative store-in-cache (SIC) in a multiprocessor (MP). The lock array enables simultaneous reset of all lock bits at each checkpoint without disturbing the associated cache directory. A special type of processor operand request, called a store-interrogate (SI) request, is used to lock the accessed line. whether or not the SI request hits or misses in the cache. Any locked line can continue to receive any fetch, SI, or store cache request from its own processor. Any line remains unlocked as long as it is not accessed by a SI request. Castout or invalidation of unlocked cache lines is performed during a checkpoint interval.

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