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    1.
    发明专利
    未知

    公开(公告)号：ES2143975T3

    公开(公告)日：2000-06-01

    申请号：ES91106051

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JOSEPH HENRY JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

    STORE-IN-CACHE MULTIPROCESSOR SYSTEM WITH CHECKPOINT FEATURE
    2.
    发明专利
    STORE-IN-CACHE MULTIPROCESSOR SYSTEM WITH CHECKPOINT FEATURE 未知

    公开(公告)号：DE3278890D1

    公开(公告)日：1988-09-22

    申请号：DE3278890

    申请日：1982-02-05

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  GERARDI JOHN ANTHONY ,  MCGILVRAY BRUCE LLOYD

    IPC: G06F12/08 ,  G06F12/12 ,  G06F15/16 ,  G06F15/177

    Abstract: A lock array (10) is provided with bit positions corresponding to each line entry in an associated cache directory (PD). When a lock bit (L) is on, it inhibits the castout, replacement, or invalidation of the associated cache line. Lock array controls (12) operate with a slot replacement selection circuit (42; which may be conventional) to eliminate each locked slot from being a replacement candidate in its congruence class in a set-associative store-in-cache (SIC) in a multiprocessor (MP). The lock array enables simultaneous reset of all lock bits at each checkpoint without disturbing the associated cache directory. A special type of processor operand request, called a store-interrogate (SI) request, is used to lock the accessed line. whether or not the SI request hits or misses in the cache. Any locked line can continue to receive any fetch, SI, or store cache request from its own processor. Any line remains unlocked as long as it is not accessed by a SI request. Castout or invalidation of unlocked cache lines is performed during a checkpoint interval.

    4.
    发明专利
    未知

    公开(公告)号：DE69132077T2

    公开(公告)日：2000-10-05

    申请号：DE69132077

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

    5.
    发明专利
    未知

    公开(公告)号：DE69132077D1

    公开(公告)日：2000-05-04

    申请号：DE69132077

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

    6.
    发明专利
    未知

    公开(公告)号：AT191295T

    公开(公告)日：2000-04-15

    申请号：AT91106051

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JOSEPH HENRY JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

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