公开(公告)号：DE3177181D1

公开(公告)日：1990-06-21

申请号：DE3177181

申请日：1981-10-05

Applicant: IBM

Inventor： CHAN SHIU KWONG ,  GERARDI JOHN ANTHONY ,  MCGILVRAY BRUCE LLOYD

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/10 ,  G06F12/1045

公开(公告)号：DE3278890D1

公开(公告)日：1988-09-22

申请号：DE3278890

申请日：1982-02-05

Applicant: IBM

Inventor： CHAN SHIU KWONG ,  GERARDI JOHN ANTHONY ,  MCGILVRAY BRUCE LLOYD

IPC: G06F12/08 ,  G06F12/12 ,  G06F15/16 ,  G06F15/177

Abstract: A lock array (10) is provided with bit positions corresponding to each line entry in an associated cache directory (PD). When a lock bit (L) is on, it inhibits the castout, replacement, or invalidation of the associated cache line. Lock array controls (12) operate with a slot replacement selection circuit (42; which may be conventional) to eliminate each locked slot from being a replacement candidate in its congruence class in a set-associative store-in-cache (SIC) in a multiprocessor (MP). The lock array enables simultaneous reset of all lock bits at each checkpoint without disturbing the associated cache directory. A special type of processor operand request, called a store-interrogate (SI) request, is used to lock the accessed line. whether or not the SI request hits or misses in the cache. Any locked line can continue to receive any fetch, SI, or store cache request from its own processor. Any line remains unlocked as long as it is not accessed by a SI request. Castout or invalidation of unlocked cache lines is performed during a checkpoint interval.

公开(公告)号：DE3176632D1

公开(公告)日：1988-03-03

申请号：DE3176632

申请日：1981-10-05

Applicant: IBM

Inventor： CHAN SHIU KWONG ,  FLUSCHE FREDERICK OTTO ,  GERARDI JOHN ANTHONY ,  GUSTAFSON RICHARD NEIL ,  MCGILVRAY BRUCE LLOYD

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/10 ,  G06F12/1045