公开(公告)号：MY127002A

公开(公告)日：2006-11-30

申请号：MYPI20005855

申请日：2000-12-13

Applicant: IBM

Inventor： BRIAN MITCHELL BASS ,  MICHAEL STEVEN SIEGEL ,  MARCO C HEDDES ,  JEAN LOUIS CALVIGNAC ,  STEVEN KENNETH JENKINS ,  MICHAEL RAYMOND TROMBLEY ,  FABRICE JEAN VERPLANKEN

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02 ,  G06F13/00 ,  G06F13/16 ,  G06F15/167 ,  G11C11/407 ,  H04L12/56

Abstract: THE ABILITY OF NETWORK PROCESSORS (50A, 50B, 50N) TO MOVE DATA TO AND FROM DYNAMIC RANDOM ACCESS MEMORY (DRAM) CHIPS (56, 58) USED COMPUTER SYSTEMS IS ENHANCED IN SEVERAL RESPECTS. IN ONE ASPECT OF THE INVENTION, TWO DOUBLE DATA RATE DRAMS ARE USED IN PARALLEL TO DOUBLE THE BANDWIDTH FOR INCREASED THROUGHPUT OF DATA. THE MOVEMENT OF DATA IS FURTHER IMPROVED BY SETTING 4 BANKS OF FULL 'READ' AND 4 BANKS OF FULL 'WRITE' BY THE NETWORK PROCESSOR FOR EVERY REPETITION OF THE DRAM TIME CLOCK. A SCHEME FOR RANDOMIZED 'READ' AND 'WRITE' ACCESS BY THE NETWORK PROCESSOR IS DISCLOSED. THIS SCHEME IS PARTICULARLY APPLICABLE TO NETWORKS SUCH AS ETHERNET THAT UTILIZE VARIABLE FRAME SIZES. (THE MOST ILLUSTRATIVE DRAWING IS FIGURE 2)

公开(公告)号：SG111013A1

公开(公告)日：2005-05-30

申请号：SG200007701

申请日：2000-12-28

Applicant: IBM

Inventor： BRIAN MITCHELL BASS ,  JEAN LOUIS CALVIGNAC ,  MARCO C HEDDES ,  MICHAEL STEVEN SIEGEL ,  MICHAEL RAYMOND TROMBLEY ,  FABRICE JEAN VERPLANKEN

IPC: G06F5/06 ,  G06F12/00 ,  G06F13/38

公开(公告)号：SG90222A1

公开(公告)日：2002-07-23

申请号：SG200007697

申请日：2000-12-28

Applicant: IBM

Inventor： BRIAN MITCHELL BASS ,  JEAN LOUIS CALVIGNAC ,  MARCO C HEDDES ,  STEVEN KENNETH JENKINS ,  MICHAEL STEVEN SIEGEL ,  MICHAEL RAYMOND TROMBLEY ,  FABRICE JEAN VERPLANKEN

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/00 ,  G06F13/16 ,  G06F15/167 ,  G11C11/407 ,  H04L12/56

Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full "read' and 4 banks of full "write' by the network processor for every repetition of the DRAM time clock. A scheme for randomized "read' and "write' access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.