公开(公告)号：EP0721164A3

公开(公告)日：1998-07-29

申请号：EP95480174

申请日：1995-12-06

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  MITCHELL OSCAR R ,  NGUYEN TUNG M ,  RIM YONJAE

IPC: H04Q3/52 ,  G06F15/173 ,  H04L12/56 ,  G06F15/16

CPC classification number: G06F15/17375 ,  H04L49/101 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/351

Abstract: A computer networking system is disclosed that includes a cross bar switch and a protocol for operating the same. The crossbar switch typically connects a plurality of ports one to another and the protocol establishes a connection between a first desired port and a second desired port selected from the plurality of ports. Each port further connects to a compute element via a master bidirectional bus and a slave bidirectional bus. Any of the compute elements can serve as either a master or slave to any other compute element connected to the crossbar switch. A master port connects the bidirectional bus to the crossbar switch and a slave port connects the slave bidirectional bus to the crossbar switch. The master port is reserved for compute element initiated operations while the slave port is reserved for network initiated operations. The crossbar switch receives and transmits control, address, and data information over a CPU bus to a network router unit, which is used as the interface between the CPU and the crossbar switch to translate CPU bus protocol to switch protocol. The crossbar switch uses an in band switch design, which excludes explicit control pins to control the switch and relies on control being transmitted over wires shared between the data and the address functions. The switch and protocol support load, store, broadcast, compare, and swap and barrier synchronization primitives, using no control pins and minimizing overhead.

公开(公告)号：CA2099413A1

公开(公告)日：1994-05-01

申请号：CA2099413

申请日：1993-06-30

Applicant: IBM

Inventor： HARDELL WILLIAM R JR ,  HENSON JAMES D JR ,  MITCHELL OSCAR R

IPC: G06F1/00 ,  G06F9/445 ,  G06F15/167 ,  G06F15/173 ,  G06F15/80 ,  G06F1/12

Abstract: An architecture and method for booting a multi-processor system having processor local memory and shared global memory, with shared global memory access managed by an atomic memory access controller and cache coherence managed by software. Reset circuits are used to synchronize to a master clock a commonly distributed start signal and processor individualized restart sequences, which reset circuit signals are distributed to reset both local and global memory. Global memory testing is assigned to a processor based upon its rate status in completing an internal test sequence. The systems and methods are particularly suited to booting a group of multiple but relatively independent processors. Furthermore, the practice of the invention facilitates booting of such system when one or more of the processors have been disconnected or failed.