公开(公告)号：EP0721164A3

公开(公告)日：1998-07-29

申请号：EP95480174

申请日：1995-12-06

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  MITCHELL OSCAR R ,  NGUYEN TUNG M ,  RIM YONJAE

IPC: H04Q3/52 ,  G06F15/173 ,  H04L12/56 ,  G06F15/16

CPC classification number: G06F15/17375 ,  H04L49/101 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/351

Abstract: A computer networking system is disclosed that includes a cross bar switch and a protocol for operating the same. The crossbar switch typically connects a plurality of ports one to another and the protocol establishes a connection between a first desired port and a second desired port selected from the plurality of ports. Each port further connects to a compute element via a master bidirectional bus and a slave bidirectional bus. Any of the compute elements can serve as either a master or slave to any other compute element connected to the crossbar switch. A master port connects the bidirectional bus to the crossbar switch and a slave port connects the slave bidirectional bus to the crossbar switch. The master port is reserved for compute element initiated operations while the slave port is reserved for network initiated operations. The crossbar switch receives and transmits control, address, and data information over a CPU bus to a network router unit, which is used as the interface between the CPU and the crossbar switch to translate CPU bus protocol to switch protocol. The crossbar switch uses an in band switch design, which excludes explicit control pins to control the switch and relies on control being transmitted over wires shared between the data and the address functions. The switch and protocol support load, store, broadcast, compare, and swap and barrier synchronization primitives, using no control pins and minimizing overhead.

公开(公告)号：CA1285654C

公开(公告)日：1991-07-02

申请号：CA570362

申请日：1988-06-24

Applicant: IBM

Inventor： COCKE JOHN ,  GROHOSKI GREGORY F ,  OKLOBDZIJA VOJIN G

IPC: G06F15/16 ,  G06F9/34 ,  G06F9/38 ,  G06F15/167 ,  G06F15/177 ,  G06F9/30

Abstract: AN INSTRUCTION CONTROL MECHANISM FOR A COMPUTING SYSTEM A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.

公开(公告)号：CA1321655C

公开(公告)日：1993-08-24

申请号：CA608713

申请日：1989-08-18

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F15/16 ,  G06F9/38 ,  G06F9/48

Abstract: AT9-88-080 TIGHTLY COUPLED MULTIPROCESSOR INSTRUCTION SYNCHRONIZATION A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：CA1313275C

公开(公告)日：1993-01-26

申请号：CA575695

申请日：1988-08-25

Applicant: IBM

Inventor： GROHOSKI GREGORY F

IPC: G06F15/16 ,  G06F9/38 ,  G06F15/80

Abstract: AT9-87-031 PARALLEL PROCESSOR INSTRUCTION DISPATCH APPARATUS WITH INTERRUPT HANDLER A data processing system for executing a sequence of instructions. The data processing system includes several processors each for executing instructions. Also included is a dispatching apparatus for dispatching each of the instructions to one of the processors. Control circuitry is included for directing the concurrent execution of the dispatched instructions in the processors irrespective of the location of the instructions in the sequence. The control circuitry includes the capability to receive an instruction interrupt signal. The control circuitry then determines which instruction generated the instruction interrupt. Upon this determination, the control circuitry resets the processors and the dispatching apparatus to the state that existed when the instruction that generated the instruction interrupt was earlier executed in order to re-execute the instruction that caused the interrupt signal in accordance with its location in the instruction sequence.

公开(公告)号：PH30201A

公开(公告)日：1997-02-05

申请号：PH39687

申请日：1989-12-13

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F9/38 ,  G06F15/16 ,  G06F9/48 ,  G06F1/00

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.