Abstract:
The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b) , at least one conductive fusible link (14) , first and second connection elements (20a, 20b) , and first and second metal lines (22a, 22b) . The conductive supporting elements (12a, 12b) , the conductive fusible link (14) , and the metal lines (22a, 22b) are located at a first metal level (3) , while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).
Abstract:
PROBLEM TO BE SOLVED: To provide structures with improved solder bump connections that prevent cracking and peeling, and to provide a method of fabricating such structures. SOLUTION: The method includes steps of: forming an upper wiring layer in dielectric layers 10, 20 and 22; and depositing one or more dielectric layers on the upper wiring layer. The method further includes a step of forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes a step of depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a structure of a control collapse chip connection (C4) and its manufacturing method, and particularly, a structure to improve reliability of lead-free C4 interconnection and its method. SOLUTION: The structure includes a ball limited metalization (BLM) layer and a solder ball of control collapse chip connection (C4) formed on the BLM layer. Moreover, the structure includes the final metal pad layer under the BLM layer and a cap layer under the final metal pad layer. Then the structure includes an air gap between the final metal pad layer and one of the BLM layer and cap layer under the C4 solder ball. COPYRIGHT: (C)2011,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide structures with improved solder bump connections and methods of fabricating such structures. SOLUTION: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
Methods of forming wire and solder bonds are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.
Abstract:
Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.