Abstract:
PROBLEM TO BE SOLVED: To provide structures with improved solder bump connections that prevent cracking and peeling, and to provide a method of fabricating such structures. SOLUTION: The method includes steps of: forming an upper wiring layer in dielectric layers 10, 20 and 22; and depositing one or more dielectric layers on the upper wiring layer. The method further includes a step of forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes a step of depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a metal wiring structure for a uniform current density in a C4 ball. SOLUTION: A sub-pad assembly of a metal structure is arranged directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure that comes into contact with the metal pad and a set of metal vias that provide electrical connection between the upper level metal line structure and a lower level metal line structure arranged underneath of the upper level metal line structure. The reliability of a C4 ball is improved by using a metal pad structure having a set of integrated metal vias that are divided and distributed to promote an uniform current density distribution in the C4 ball. The areal density of the cross-sectional area of the plurality of metal vias is higher at the center part of the metal pad than at the peripheral edge part of the flat part of the metal pad. COPYRIGHT: (C)2011,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a structure of a control collapse chip connection (C4) and its manufacturing method, and particularly, a structure to improve reliability of lead-free C4 interconnection and its method. SOLUTION: The structure includes a ball limited metalization (BLM) layer and a solder ball of control collapse chip connection (C4) formed on the BLM layer. Moreover, the structure includes the final metal pad layer under the BLM layer and a cap layer under the final metal pad layer. Then the structure includes an air gap between the final metal pad layer and one of the BLM layer and cap layer under the C4 solder ball. COPYRIGHT: (C)2011,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide structures with improved solder bump connections and methods of fabricating such structures. SOLUTION: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a highly reliable copper structure for improving current carrying capabilities (e.g., current spreading) of an interconnect, and to provide a method of fabricating the same. SOLUTION: The interconnect structure provides a highly reliable copper interconnect structure for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: one adhesion layer; one plated barrier layer; and one plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy. COPYRIGHT: (C)2011,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a technique of selectively removing a material, which is used at the time of forming an electronic module, constituted of a 'stack' of a plurality of chips, from a cut groove region (kerf region) related to the semiconductor chips. SOLUTION: This method includes a method of providing a wafer having a plurality of integrated circuit chips having a cut groove region 17 between them. Chip metallized films 15 and 16 exist in the region 17. The wafer is protected using a photolithographic process, and only the region 17 is exposed. Then, the wafer is etched, and the chip metallized films are removed from the region 17. Then the wafer is diced, and the chips are stacked to form a monolithic electronic module. The side surfaces of the module are treated to expose a transfer metallic film which extends to the side surfaces of the module. Thereby, the electrical connection of the transfer metallic film to the chips in the module is facilitated.
Abstract:
Methods of forming wire and solder bonds are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region. Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.
Abstract:
Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.