公开(公告)号：WO2007131867B1

公开(公告)日：2008-03-06

申请号：PCT/EP2007054077

申请日：2007-04-25

Applicant: IBM ,  IBM UK ,  JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

Inventor： JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二触点到器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

公开(公告)号：EP2024997A4

公开(公告)日：2009-12-16

申请号：EP07797486

申请日：2007-05-16

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2007311797A

公开(公告)日：2007-11-29

申请号：JP2007130660

申请日：2007-05-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAMBINO JEFFREY PETER ,  SON VAN NGUYEN

IPC: H01L27/10 ,  H01L29/06

CPC classification number: B82Y10/00 ,  G11C13/025 ,  H01L21/7682 ,  H01L29/0665 ,  H01L29/685 ,  H01L29/86 ,  H01L51/0048 ,  H01L51/0554 ,  H01L2221/1094

Abstract: PROBLEM TO BE SOLVED: To provide an encapsulated nanotube structure for protecting a semiconductor device formed on an electrical structure, from an external factor. SOLUTION: A semiconductor device includes a conductive nanotube formed on a first conductive member, so that a first gap exists between a lower side of the conductive nanotube and an upper side of the first conductive member. A second insulating layer is formed on the conductive nanotube. A second gap exists between the upper side of the conductive nanotube and a first part of the second insulating layer. A first via opening and a second via opening are respectively passed through the second insulating layer and extended into the second gap. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于保护形成在电气结构上的半导体器件与外部因素的封装的纳米管结构。 解决方案：半导体器件包括形成在第一导电构件上的导电纳米管，使得在导电纳米管的下侧和第一导电构件的上侧之间存在第一间隙。 在导电性纳米管上形成第二绝缘层。 在导电性纳米管的上侧和第二绝缘层的第一部分之间存在第二间隙。 第一通孔开口和第二通孔开口分别穿过第二绝缘层并延伸到第二间隙中。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007221134A

公开(公告)日：2007-08-30

申请号：JP2007031779

申请日：2007-02-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MARK D JAFFE ,  RICHARD J RASSEL ,  ADKISSON JAMES WILLIAM ,  GAMBINO JEFFREY PETER ,  LOISEAU ALAN

IPC: H01L27/146 ,  H01L27/14 ,  H04N5/335

CPC classification number: H01L27/14643 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14689

Abstract: PROBLEM TO BE SOLVED: To provide an imaging sensor having an array of FET pixels, and a method of forming the imaging sensor. SOLUTION: Each pixel is a semiconductor island such as N-type silicon on a silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode such as a P-well cathode. A color filter may be attached to an opposite surface of the island. A protective layer (such as a glass or quartz layer) or a protective window is fixed to the pixel array at the color filter. An imaging sensor may be illuminated from the backside with cell wiring above a cell. Thus, an optical signal passing through the protective layer is filtered by the color filter and is selectively sensed by a corresponding photo-sensor. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有FET像素阵列的成像传感器以及形成该成像传感器的方法。 解决方案：每个像素是绝缘体上硅（SOI）晶片上的半导体岛，例如N型硅。 FET形成在诸如P阱阴极的一个光电二极管电极中。 滤色器可以附接到岛的相对表面。 保护层（例如玻璃或石英层）或保护窗被固定在滤色器的像素阵列上。 可以从背面照射成像传感器，其中电池布线在电池单元上方。 因此，通过保护层的光信号被滤色器滤掉，并被相应的光传感器选择性地感测。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO0245134A3

公开(公告)日：2003-04-03

申请号：PCT/US0151214

申请日：2001-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  WEYBRIGHT MARY E ,  HORN PETER ,  BRONNER GARY ,  CONTI RICHARD A ,  SCHROEDER UWE ,  GAMBINO JEFFREY PETER

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

Abstract: Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Abstract translation: 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：WO2007137049A3

公开(公告)日：2008-01-31

申请号：PCT/US2007069002

申请日：2007-05-16

Applicant: IBM ,  BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成在下晶片（100A）中的器件（130A），并且布线层（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。

公开(公告)号：JP2008141014A

公开(公告)日：2008-06-19

申请号：JP2006326348

申请日：2006-12-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RASSEL RICHARD JOHN ,  GAMBINO JEFFREY PETER ,  ADKISSON JAMES WILLIAM ,  LEIDY ROBERT KENNETH

IPC: H01L27/14

Abstract: PROBLEM TO BE SOLVED: To provide an optical sensor structure and a method for forming the structure.
SOLUTION: The optical sensor structure contains (a) a semiconductor substrate and (b) a light-collecting region on the semiconductor substrate. Also, the optical sensor structure contains a funnel-shaped optical pipe on the light-collecting region. The funnel-shaped optical pipe contains (i) a lower cylindrical portion on the light-collecting region and (ii) a funnel-shaped portion, having a tapering shape and arranged on the lower cylindrical portion, while physically coming into direct contact with the lower cylindrical portion. This structure further contains a color filter region on the funnel-shaped optical pipe.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种光学传感器结构和形成该结构的方法。 解决方案：光学传感器结构包含（a）半导体衬底和（b）半导体衬底上的聚光区域。 此外，光学传感器结构在光收集区域上包含漏斗形光管。 漏斗状光学管道包括（i）集光区域上的下圆筒部分和（ii）锥形部分，其具有锥形形状并且布置在下圆柱形部分上，同时物理上直接接触 下圆柱形部分。 该结构还在漏斗状的光导管上含有滤色器区域。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2001077321A

公开(公告)日：2001-03-23

申请号：JP2000220495

申请日：2000-07-21

Applicant: IBM

Inventor： GARY B BRONER ,  GAMBINO JEFFREY PETER ,  RADENS CARL J

IPC: B24B37/04 ,  H01L21/027 ,  H01L21/28 ,  H01L21/304 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To realize a process for manufacturing two kinds of different gate dielectric thicknesses by using a polysilicon mask and chemical mechanical polishing(CMP). SOLUTION: A thick gate dielectric 102 is grown on a substrate having a memory array area 201 and a logical device area 101, and a gate stack containing a first polysilicon layer 103 is formed on the dielectric 102. Then a thin gate dielectric 200 is formed on the substrate above the logical device area 101, and a second polysilicon layer 300 is formed in the logical device area 101. The thickness of the second polysilicon layer 300 is at least made to be equal to that of the gate stack in the memory array area 201. The structure is flattened by using chemical mechanical polishing(CMP), and the gate stack in the memory array area 201 and logical device area 101 is patterned.

公开(公告)号：JP2002016070A

公开(公告)日：2002-01-18

申请号：JP2001171050

申请日：2001-06-06

Applicant: IBM

Inventor： LAWRENCE ALFRED CLEVENGER ,  RONALD JEAN PHILIPPI ,  RODBELL KENNETH PARKER ,  ROY CHARLES IGGULDEN ,  CHAOKUN FUU ,  LINN MARIE GIGNAC ,  WEBER STEPHAN ,  GAMBINO JEFFREY PETER ,  SCHNABEL RAINER FLORIAN

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a dual damascene process that can reliably form aluminum interconnection exhibiting improved electro migration characteristics, as compared with aluminum interconnection that is formed by the conventional RIE technique. SOLUTION: More specifically, the dual damascene process depends on a PVD-Ti/CVD-TiN barrier layer and forms an aluminum line showing great reduction in a saturation resistance level, the inhibition of the electro migration, or both of them especially in a line longer than 100 micrometers. The electromigration life time of the dual damascene aluminum line depends greatly on the conditions of materials and material-filling processes. When there is deviation in the materials and treatment, the electromigration life time way possibly become shorter than life time that is achieved by an aluminum RIE interconnection line, and this becomes a serious matter.

公开(公告)号：JPH10135326A

公开(公告)日：1998-05-22

申请号：JP27283597

申请日：1997-10-06

Applicant: IBM ,  SIEMENS AG

Inventor： GAMBINO JEFFREY PETER ,  NGUYEN SON VAN ,  STENGL REINHARD

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To increase the densities of borophosphate-silicate glass and an oxide existing on the glass before forming a pattern, by exposing the glass and undoped oxide to a high temperature before a line patterning step, a contact etching step, and an ion implanting step. SOLUTION: After a dielectric layer of borophosphate-silicate glass having fluidity is stuck to the surface of a substrate, another dielectric layer of a material having no fluidity is stuck to the surface of the glass layer. Then, contact etching and a high dose of ion implantation are performed so that an undoped oxide composed of SiO2 existing on the dielectric layer having no fluidity can be exposed to a junction activating annealing temperature, namely, a high annealing temperature of about 800 deg.C to 1,100 deg.C. After the ion implantation, contacts and lines are metallized by again exposing the contacts and lines to a high annealing temperature. Therefore, the densities of the borophosphate-silicate glass and SiO2 existing on the glass can be increased before forming a pattern.