公开(公告)号：JPH09307407A

公开(公告)日：1997-11-28

申请号：JP11470496

申请日：1996-05-09

Applicant: IBM

Inventor： IOKI KAZUYA ,  NISHIHARA MICHITETSU

IPC: H03K3/03 ,  H03K5/00 ,  H03K5/15 ,  H03L7/07 ,  H03L7/081

Abstract: PROBLEM TO BE SOLVED: To reduce consuming area, to improve the stability, to attain a high convergence speed and to avoid problems for mount and correspondence to a design change by adopting a digital circuit for a clock oscillator. SOLUTION: A delay element chain 20 is formed by connecting an array of 2-stage inverters 22 as a delay element in series. A delay element selection section 30 such as a shift register to store bits to indicate a selecting state is connected to each array of the inverters 22 as a means to select a desired array of the inverters 22. The delay element chain 20 is connected to an external clock 1 via an input logic circuit 7. A wiring 40 is used to form a proper closed loop between the selected array of the inverters 22 and the input logic circuit 7. Since number of the delay elements included in the closed loop differs depending which of the array is selected among the arrays of the inverters 22 connected in series, the oscillating frequency of the clock oscillator is changed.

公开(公告)号：JPH01143255A

公开(公告)日：1989-06-05

申请号：JP28229187

申请日：1987-11-10

Applicant: IBM

Inventor： NISHIHARA MICHITETSU ,  SUNANAGA TOSHIO

IPC: H01L29/78 ,  G11C17/00 ,  G11C17/08 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112

Abstract: PURPOSE: To obtain a read only memory wherein density is high, manufacturing cost is low, and row selection/sensing constitution is simple, by applying one out of four states of a diffusion region which has the same conductivity type as a substrate and impurity layer concentration higher than the substrate and a channel region part. CONSTITUTION: An FET of a memory cell is programed by applying one out of four kinds of P impurity diffusion patterns to a channel region. The four kinds of diffusion patterns are (A) a case wherein P impurity diffusion region is not contained in the channel region, (B) a case wherein a P impurity diffusion region 30 is contained only in a channel region part of the drain 20 side, (C) a case wherein a P impurity diffusion region 32 is contained only in a channel region part of the source 22 side, (D) a case wherein a P impurity diffusion region 34 is contained in both of the channel region parts of the drain side and the source side. When the above combination is properly set, one out of four saturation currents can be generated in one direction. The FET's have the same dimension, and the respective P impurity diffusion regions can have the same impurity density by using the minimum design rule. Manufacturing is enabled one time with a masking/P ion implantation process.