公开(公告)号：JP2007234225A

公开(公告)日：2007-09-13

申请号：JP2007154901

申请日：2007-06-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

IPC: G11C11/401 ,  G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/409

CPC classification number: G06F12/0893 ,  G11C7/1006 ,  G11C2207/2245

Abstract: PROBLEM TO BE SOLVED: To improve access cycle time of a dynamic random access memory (DRAM) system having a plurality of memory cells constituted of rows and columns.
SOLUTION: A method comprises a step in which a destructive read mode is enabled, the destruction read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write-back-mode is enabled, this delay write-back-mode is a mode for restoring bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：改进具有由行和列构成的多个存储单元的动态随机存取存储器（DRAM）系统的访问周期时间。 解决方案：一种方法包括其中启用破坏性读取模式的步骤，破坏读取模式是用于破坏性地读出存储在正在寻址的DRAM存储器单元中的一位信息的模式。 信息被破坏性读取的位临时存储在临时存储装置中。 延迟回写模式被使能，该延迟写回模式是用于恢复之后寻址的DRAM存储单元中的信息位的模式。 然后，根据临时存储设备中的空间的可用性来调度延迟写回模式的执行。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002334580A

公开(公告)日：2002-11-22

申请号：JP2002121334

申请日：2002-04-23

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

IPC: G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling operation of a dynamic random access memory(DRAM) system having a plurality of memory cells constituted of rows and columns. SOLUTION: This method comprises a step in which a destructive read mode is enabled, the destructive read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write.back.mode is enabled, this delay write-back-mode is a mode for restore bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.

公开(公告)号：JP2002334579A

公开(公告)日：2002-11-22

申请号：JP2002104679

申请日：2002-04-08

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG H ,  OH HWA-JOON

IPC: G11C11/409 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving write time for a dynamic random access memory(DRAM) having destructive read architecture. SOLUTION: This method is a method for prepairing dynamic random access memory(DRAM) cells for write operation having a condition previously set. This method comprises that a voltage level previously set in a cell is made before delay-rewriting in destructive read architecture, and this voltage level previously set has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when 0 bit is stored in a cell, the logic 1 voltage level corresponds to a second cell voltage value when 1 bit is stored in a cell. Before a voltage level previously set is made in a cell, the cell has an initial voltage value corresponding to either of the logic 0 voltage level or the logic 1 voltage level.