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    SYSTEM AND METHOD FOR A MEMORY WITH COMBINED LINE AND WORD ACCESS
    1.
    发明申请
    SYSTEM AND METHOD FOR A MEMORY WITH COMBINED LINE AND WORD ACCESS 审中-公开
    具有组合线和字访问的存储器的系统和方法

    公开(公告)号：WO2006082154A2

    公开(公告)日：2006-08-10

    申请号：PCT/EP2006050433

    申请日：2006-01-25

    Applicant: IBM ,  IBM UK ,  DHONG SANG HOO ,  FLACHS BRIAN KING ,  HOFSTEE HARM PETER ,  TAKAHASHI OSAMU

    Inventor： DHONG SANG HOO ,  FLACHS BRIAN KING ,  HOFSTEE HARM PETER ,  TAKAHASHI OSAMU

    IPC: G06F13/16

    CPC classification number: G06F13/28 ,  G06F13/1626 ,  G06F13/1663

    Abstract: A system and method for a processor with memory with combined line and word access are presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

    Abstract translation: 提出了一种具有组合线和字访问的存储器的处理器的系统和方法。 系统执行窄读/写存储器访问，并使用多路复用器和锁存器对同一存储体进行宽读/写存储器访问以指导数据。 该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。 在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。 通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

    Destructive read architecture for dynamic random access memory
    2.
    发明专利
    Destructive read architecture for dynamic random access memory 有权
    用于动态随机访问记忆的破坏性阅读架构

    公开(公告)号：JP2007234225A

    公开(公告)日：2007-09-13

    申请号：JP2007154901

    申请日：2007-06-12

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

    IPC: G11C11/401 ,  G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/409

    CPC classification number: G06F12/0893 ,  G11C7/1006 ,  G11C2207/2245

    Abstract: PROBLEM TO BE SOLVED: To improve access cycle time of a dynamic random access memory (DRAM) system having a plurality of memory cells constituted of rows and columns.
    SOLUTION: A method comprises a step in which a destructive read mode is enabled, the destruction read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write-back-mode is enabled, this delay write-back-mode is a mode for restoring bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：改进具有由行和列构成的多个存储单元的动态随机存取存储器（DRAM）系统的访问周期时间。 解决方案：一种方法包括其中启用破坏性读取模式的步骤，破坏读取模式是用于破坏性地读出存储在正在寻址的DRAM存储器单元中的一位信息的模式。 信息被破坏性读取的位临时存储在临时存储装置中。 延迟回写模式被使能，该延迟写回模式是用于恢复之后寻址的DRAM存储单元中的信息位的模式。 然后，根据临时存储设备中的空间的可用性来调度延迟写回模式的执行。 版权所有（C）2007，JPO＆INPIT

    ACCESS METHOD TO MEMORY AND MEMORY
    3.
    发明专利
    ACCESS METHOD TO MEMORY AND MEMORY 审中-公开

    公开(公告)号：JP2002073412A

    公开(公告)日：2002-03-12

    申请号：JP2001213766

    申请日：2001-07-13

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HOFSTEE HARM PETER ,  TAKAHASHI OSAMU ,  LUNTEREN JAN VAN

    IPC: G06F12/02 ,  G06F12/06

    Abstract: PROBLEM TO BE SOLVED: To disclose a method to implement an address mapping for a memory in a computer system. SOLUTION: The memory is composed of several memory banks and each memory bank identifies itself with each bank number. A block address component of a physical address is converted into a corresponding bank number and a related internal bank address. The bank number is constituted by connecting a fist lookup table output with a second lookup table output. The output of the first table is obtained by a first segment X1 and a second segment Y1 of the block address component and the output of the second table is obtained by a third segment X2 and a fourth segment Y2 of the block address component. Data saved at a specified location can be accessed by means of the bank number and the related internal bank address.

    Programmable logic array in which wire is trimmed
    4.
    发明专利
    Programmable logic array in which wire is trimmed 有权
    可编程逻辑阵列在线被修剪

    公开(公告)号：JP2005045221A

    公开(公告)日：2005-02-17

    申请号：JP2004180883

    申请日：2004-06-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BUCKI ROBERT JOHN ,  DHONG SANG HOO ,  JOEL ABRAHAM SILVERMAN ,  OSAMU TAKAHASHI

    IPC: H01L21/82 ,  G06F17/50 ,  H03K19/00 ,  H03K19/177

    CPC classification number: G06F17/5054

    Abstract: PROBLEM TO BE SOLVED: To shorten a signal delay and lower a power consumption by customizing a wire-segment length in a programmable logic array so that a parasitic capacitance related to an interconnection line is minimized.
    SOLUTION: A first array composed of a junction leaf cell is constituted so that tiles are arranged by using at least one 1-cell and at least one 0-cell, and at least one logical expression is defined by the relative positional relationship of mutual cells configuring the array. The interconnection lines in which lengths are optimized are added to the array. Each interconnection line in which the lengths are optimized is ended by the leaf cell in the array, with which the interconnection lines are brought into contact lastly. The leaf cell can be used as a floating leaf cell. In the floating leaf cell, a pair of any junction leaf cells are electrically insulated mutually until the interconnection lines in which the lengths are optimized are added to the constitution.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：通过定制可编程逻辑阵列中的线段长度来缩短信号延迟并降低功耗，使得与互连线相关的寄生电容最小化。 解决方案：由结叶单元组成的第一阵列被构造成使得通过使用至少一个1单元和至少一个0单元布置瓦片，并且至少一个逻辑表达式由相对位置关系 的相互单元配置阵列。 将长度优化的互连线添加到阵列中。 长度优化的每个互连线由阵列中的叶单元结束，最后互连线与之接触。 叶细胞可以用作浮叶细胞。 在浮动叶细胞中，一对任何连接叶细胞相互电绝缘，直到将长度优化的互连线添加到构造中。 版权所有（C）2005，JPO＆NCIPI

    METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT
    5.
    发明申请
    METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT 审中-公开
    减少SOI电路漏电流的方法和装置

    公开(公告)号：WO2006127495A3

    公开(公告)日：2007-06-07

    申请号：PCT/US2006019534

    申请日：2006-05-19

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM ,  TOSHIBA AMERICA ELECTRONIC

    Inventor： YOSHIHARA HIROSHI ,  DHONG SANG HOO ,  TAKAHASHI OSAMU ,  NAKAZATO TAKAAKI

    IPC: H03K19/00 ,  H03K17/16

    CPC classification number: H03K19/0016

    Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially- equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on- insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node .

    Abstract translation: 方法和设备通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中， 使用绝缘体上硅（SOI）布置中的多个晶体管实现数字电路，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

    Level shifter for boosting wordline voltage and memory cell performance
    6.
    发明专利
    Level shifter for boosting wordline voltage and memory cell performance 有权
    提高字线电压和存储单元性能的级别更换

    公开(公告)号：JP2009118466A

    公开(公告)日：2009-05-28

    申请号：JP2008252263

    申请日：2008-09-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOSHI RAJIV VASANT ,  DHONG SANG HOO ,  JUERGEN PILLE ,  OSAMU TAKAHASHI ,  SCOTT RAYMOND COTTIER

    IPC: H03K19/0185 ,  H01L21/82 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

    CPC classification number: G11C8/08 ,  G11C11/418

    Abstract: PROBLEM TO BE SOLVED: To provide a level shifter for boosting a wordline voltage and memory cell performance without making a circuit defective in operation or without causing excessive leakage. SOLUTION: A circuit and a method include a first circuit powered by a first supply voltage and second a circuit powered by a second supply voltage. A level shifter is coupled between the first circuit and the second circuit. The level shifter is configured so that a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage is selected according to an input signal which depends on at least one of an operation to be performed and a component performing the operation. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于提高字线电压和存储单元性能的电平移位器，而不会使电路在操作中有缺陷或不引起过度泄漏。 解决方案：电路和方法包括由第一电源电压供电的第一电路，以及由第二电源电压供电的第二电路。 电平移位器耦合在第一电路和第二电路之间。 电平移位器被配置为使得根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，该输入信号取决于要执行的操作和执行操作的组件中的至少一个 操作。 版权所有（C）2009，JPO＆INPIT

    DESTRUCTIVE READ ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORY
    7.
    发明专利
    DESTRUCTIVE READ ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：JP2002334580A

    公开(公告)日：2002-11-22

    申请号：JP2002121334

    申请日：2002-04-23

    Applicant: IBM

    Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

    IPC: G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling operation of a dynamic random access memory(DRAM) system having a plurality of memory cells constituted of rows and columns. SOLUTION: This method comprises a step in which a destructive read mode is enabled, the destructive read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write.back.mode is enabled, this delay write-back-mode is a mode for restore bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.

    METHOD AND DEVICE FOR MOUNTING LOGIC BY USING MASK PROGRAMMABLE DYNAMIC LOGIC GATE
    9.
    发明专利
    METHOD AND DEVICE FOR MOUNTING LOGIC BY USING MASK PROGRAMMABLE DYNAMIC LOGIC GATE 失效

    公开(公告)号：JP2002009612A

    公开(公告)日：2002-01-11

    申请号：JP2001136609

    申请日：2001-05-07

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  NGO HUNG CAI ,  PARK JAEHONG ,  OSAMU TAKAHASHI

    IPC: H01L21/82 ,  H03K19/173

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for mounting dynamic logic having a dynamic programmable logic gate. SOLUTION: The method and the device activate so as to complement a programmable logic array(PLA) used for a high-speed microprocessor design. A matrix, consisting of selectable cells permits powerful logic functions such as AND-OR gate functions with a minimum possible number of entries and of transistors(TRs). Employing the programmable logic array and a dynamic programmable gate can considerably improve the efficiency of logic blocks almost, without the need for adding of the circuit region.

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