公开(公告)号：WO2005001839A3

公开(公告)日：2005-05-12

申请号：PCT/EP2004051148

申请日：2004-06-17

Applicant: IBM ,  IBM UK ,  WORDEMAN MATTHEW ,  BARTH JOHN ,  KIRIHATA TOSHIAKI

Inventor： WORDEMAN MATTHEW ,  BARTH JOHN ,  KIRIHATA TOSHIAKI

IPC: G11C7/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C8/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/40603 ,  G11C11/40615

Abstract: A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to'pipeline'the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-Eke cycle and access times with a smaller and more SER immune memory cell.

Abstract translation: 描述了利用单端双端口破坏性写存储器单元和本地回写缓冲器的存储架构。 每个单元都具有单独的读取和写入端口，可以从阵列中的一个字线上的单元读出数据，随后将其写回到这些单元，同时读出数组中另一个字线上的单元格。 通过实现读出放大器阵列，使得一个放大器耦合到每个读取位线，并且锁存器接收感测数据的结果并将该数据传送到写入数据线，可以“读取”和 读周期的回写阶段。 这允许来自一个周期的回写阶段与另一个周期的读出阶段同时发生。 通过扩展锁存器的操作以接受来自读出放大器或由存储器数据输入的数据，由列地址和掩码位修改，还可以管理读出和修改回写阶段 的写周期，允许它们同时发生。 该架构优选采用诸如2T或3T增益单元的非破坏性读取存储器单元，利用更小和更多的SER免疫存储器单元实现SRAM-Eke循环和访问时间。

公开(公告)号：JP2007234225A

公开(公告)日：2007-09-13

申请号：JP2007154901

申请日：2007-06-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

IPC: G11C11/401 ,  G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/409

CPC classification number: G06F12/0893 ,  G11C7/1006 ,  G11C2207/2245

Abstract: PROBLEM TO BE SOLVED: To improve access cycle time of a dynamic random access memory (DRAM) system having a plurality of memory cells constituted of rows and columns.
SOLUTION: A method comprises a step in which a destructive read mode is enabled, the destruction read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write-back-mode is enabled, this delay write-back-mode is a mode for restoring bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：改进具有由行和列构成的多个存储单元的动态随机存取存储器（DRAM）系统的访问周期时间。 解决方案：一种方法包括其中启用破坏性读取模式的步骤，破坏读取模式是用于破坏性地读出存储在正在寻址的DRAM存储器单元中的一位信息的模式。 信息被破坏性读取的位临时存储在临时存储装置中。 延迟回写模式被使能，该延迟写回模式是用于恢复之后寻址的DRAM存储单元中的信息位的模式。 然后，根据临时存储设备中的空间的可用性来调度延迟写回模式的执行。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002334580A

公开(公告)日：2002-11-22

申请号：JP2002121334

申请日：2002-04-23

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

IPC: G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling operation of a dynamic random access memory(DRAM) system having a plurality of memory cells constituted of rows and columns. SOLUTION: This method comprises a step in which a destructive read mode is enabled, the destructive read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write.back.mode is enabled, this delay write-back-mode is a mode for restore bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.