公开(公告)号：EP1436843A4

公开(公告)日：2008-11-26

申请号：EP02780350

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L29/76 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the 'body-to-source' voltage.

公开(公告)号：JP2000058779A

公开(公告)日：2000-02-25

申请号：JP21476499

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  PARK BYEONGJU ,  RADENS CARL J ,  SCHREMS MARTIN E

IPC: H01L21/02 ,  H01L21/3215 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a trench capacitor structure suited for use in a semiconductor integrated circuit device and also provide a process sequence used for forming the structure. SOLUTION: A trench structure wherein a trench is demarcated in a semiconductor substrate 100 includes a trench wall, a silicon buried plate 14 doped with conductive species existing in part of the semiconductor substrate around the trench wall, and a silicon structure with texture formed along part of the trench wall. This trench capacitor has improved capacitance by including a capacitor plate constituted of semispherical silicons with texture.

公开(公告)号：WO2008109654A3

公开(公告)日：2008-11-06

申请号：PCT/US2008055875

申请日：2008-03-03

Applicant: IBM ,  CESTERO ALBERTO ,  PARK BYEONGJU ,  SAFRAN JOHN M

Inventor： CESTERO ALBERTO ,  PARK BYEONGJU ,  SAFRAN JOHN M

IPC: H01L21/82 ,  H01L21/326

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antifuse (100) having a link (125) including a region (150) of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode (120) into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode (120) and anode (110) are preferably shaped to control regions from which and to which material is electrically migrated After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures

Abstract translation: 具有包括非硅化半导体材料的区域（150）的链路（125）的反熔丝（100）可以以降低的电压和电流被编程，并且通过金属或硅化物从阴极（120）的电迁移到区域 的非硅化半导体材料以形成具有降低的体积电阻的合金。 阴极（120）和阳极（110）优选地被成形为控制从哪个材料和哪些材料电迁移的区域。在编程之后，材料的额外的电迁移可将反熔丝返回到高电阻状态。 反熔丝制造的过程与场效应晶体管的制造完全兼容，并且反熔丝可有利地形成在隔离结构上

公开(公告)号：WO03025977A3

公开(公告)日：2003-08-14

申请号：PCT/US0230369

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

Abstract translation: 本发明涉及包括具有上表面和彼此相对的第一和第二侧表面的衬底的缠绕栅极晶体管。 源极和漏极区域（28）形成在衬底中，其间具有沟道区域。 沟道区域从衬底的第一侧表面延伸到第二侧表面。 栅极电介质层（40）形成在衬底上。 栅极电极（42）形成在栅极电介质层（40）上，以从上表面和第一和第二侧表面覆盖沟道区域，栅电介质（40）位于它们之间。 衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛（12），并且具有包括第一和第二侧表面的四个侧表面。 源极和漏极区域（28）形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。 包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。

公开(公告)号：AU2002343408A1

公开(公告)日：2003-04-01

申请号：AU2002343408

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

Abstract: A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the "body-to-source" voltage.

公开(公告)号：MY126185A

公开(公告)日：2006-09-29

申请号：MYPI20023100

申请日：2002-08-22

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK A

IPC: H01L29/41 ,  H01L21/336 ,  H01L29/94 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L31/113

Abstract: A WRAPPED-GATE TRANSISTOR INCLUDES A SUBSTRATE HAVING AN UPPER SURFACE AND FIRST AND SECOND SIDE SURFACES OPPOSING TO EACH OTHER.SOURCE AND DRAIN REGIONS (28) ARE FORMED IN THE SUBSTRATE WITH A CHANNEL REGION THEREBETWEEN. THE CHANNEL REGION EXTENDS FROM THE FIRST SIDE SURFACE TO THE SECOND SIDE SURFACES OF THE SUBSTRATE. A GATE DIELECTRIC LAYER (40) IS FORMED ON THE SUBSTRATE. A GATE ELECTRODE (42) IS FORMED ON THE GATE DIELECTRIC LAYER TO COVER THE CHANNEL REGION FROM THE UPPER SURFACE AND THE FIRST AND SECOND SIDE SURFACES WITH THE GATE DIELECTRIC THEREBETWEEN. THE SUBSTRATE IS A SILICON ISLAND FORMED ON AN INSULATION LAYER OF AN SOI (SILICON-ON-INSULATOR) SUBSTRATE OR ON A CONVENTIONAL NON-SOI SUBSTRATE, AND HAS FOUR SIDE SURFACES INCLUDING THE FIRST AND SECOND SIDE SURFACES. THE SOURCE AND DRAIN REGIONS ARE FORMED ON THE PORTIONS OF THE SUBSTRATE ADJOINING THE THIRD AND FOURTH SIDE SURFACES WHICH ARE PERPENDICULAR TO THE FIRST AND SECOND SIDE SURFACES. THE WRAPPEDGATE STRUCTURE PROVIDES A BETTER AND QUICKER POTENTIAL CONTROL WITHIN THE CHANNEL AREA, WHICH YIELDS STEEP SUB-THRESHOLD SLOPE AND LOW SENSITIVITY TO THE "BODY-TO-SOURCE" VOLTAGE.(FIG 18A)