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    AN INTERMEDIATE MANUFACTURE FOR A DUAL GATE LOGIC DEVICE
    2.
    发明申请
    AN INTERMEDIATE MANUFACTURE FOR A DUAL GATE LOGIC DEVICE 审中-公开
    双门逻辑器件的中间制造

    公开(公告)号：WO02101834A3

    公开(公告)日：2003-05-30

    申请号：PCT/GB0202622

    申请日：2002-05-30

    Applicant: IBM ,  IBM UK

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  MA WILLIAM

    IPC: H01L21/76 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49

    CPC classification number: H01L29/66484 ,  H01L21/2807 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648

    Abstract: The present invention features double-or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.

    Abstract translation: 本发明的特征在于双栅极或双栅极逻辑器件，其包含始终自对准并且具有恒定宽度的沟道的栅极导体。 本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。 以这种方式，可以将栅极导体封装在介电壳中，而不改变硅沟道的长度。 采用单晶硅晶片作为通道材料。 自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。 通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。 描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。

    IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING
    3.
    发明申请
    IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING 审中-公开
    具有防护光学涂层的浸没式光学光刻系统

    公开(公告)号：WO2007039374A3

    公开(公告)日：2007-07-05

    申请号：PCT/EP2006065995

    申请日：2006-09-05

    Applicant: IBM ,  IBM UK ,  HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

    Inventor： HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

    IPC: G03F7/20 ,  G03F7/11

    CPC classification number: G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

    Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

    Abstract translation: 提供浸没式光刻系统，其包括可操作以产生具有标称波长的光的光源和光学成像系统。 光学成像系统在从光源到要被图案化的物品的光路中具有光学元件。 光学元件具有适于接触占据面部和物品之间的空间的液体的面。 光学元件包括可通过液体降解的材料和覆盖可降解材料的表面以保护表面免受液体影响的保护涂层，保护涂层对光线是透明的，当暴露于光时稳定并且稳定时 暴露于液体。

    METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY
    4.
    发明公开
    METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY 审中-公开
    METHOD FOR SEPARATE OPTIMIZE在同一半导体芯片的PMOS和NMOS晶体管薄栅极电介质，因此生产的设备

    公开(公告)号：EP1668696A4

    公开(公告)日：2008-09-03

    申请号：EP04783206

    申请日：2004-09-07

    Applicant: IBM

    Inventor： CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  VAREKAMP PATRICK R ,  SLEIGHT JEFFREY W ,  SEKIGUCHI AKIHISA

    IPC: H01L21/8238

    CPC classification number: H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

    Abstract: A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.

    METHOD FOR WRAPPED-GATE MOSFET
    5.
    发明公开
    METHOD FOR WRAPPED-GATE MOSFET 审中-公开
    方法包裹的栅极MOSFET

    公开(公告)号：EP1436843A4

    公开(公告)日：2008-11-26

    申请号：EP02780350

    申请日：2002-09-17

    Applicant: IBM

    Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

    IPC: H01L29/41 ,  H01L29/76 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

    Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the 'body-to-source' voltage.

    IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING
    9.
    发明申请
    IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING 审中-公开
    具有保护光学涂层的光学光刻系统

    公开(公告)号：WO2007039374B1

    公开(公告)日：2007-08-30

    申请号：PCT/EP2006065995

    申请日：2006-09-05

    Applicant: IBM ,  IBM UK ,  HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

    Inventor： HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES III ,  MOUMEN NAIM

    IPC: G03F7/20 ,  G03F7/11

    CPC classification number: G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

    Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

    Abstract translation: 提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。 光学成像系统具有从光源到待图案化的制品的光路中的光学元件。 光学元件具有适于接触占据面部和制品之间的空间的液体的面。 光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时 暴露于液体。

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