公开(公告)号：JP2002043581A

公开(公告)日：2002-02-08

申请号：JP2001154502

申请日：2001-05-23

Applicant: IBM

Inventor： JAMES W ADKISSON ,  PAUL D ANGELO ,  BALLANTINE ARNE W ,  CHRISTOPHER S PUTNAM ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual/wrap-around gate field effect transistor particularly having a short gage length, a low off current and good performance and a method for manufacturing the same. SOLUTION: In the field effect transistor comprising gates each having a length of 10 nm or less and a conductive channel having a width maintained at 1/2 to 1/4 of the length of the gate so that the gates are disposed at least at two sides of the channel, a device having a complete depletion layer is formed without considering the off current. The above-mentioned channel is obtained by forming a groove in a minimum lithographic size, forming sidewalls in the groove and etching a gate structure in a self-alignment manner with the sidewalls. The channel is thereafter epitaxially grown from a source structure in the groove so that the source, the channel and a drain region are integrated in a single crystal structure.