公开(公告)号：JPH11329999A

公开(公告)日：1999-11-30

申请号：JP7760399

申请日：1999-03-23

Applicant: IBM

Inventor： JAMES W ADKISSON ,  JEROME B LASKEY ,  PAUL W PASTEL ,  JEDDO H RANKIN

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide an advanced method for forming flat separate areas between devices. SOLUTION: An oxygen injection 5 is performed to form a buried oxide layer in a substrate 4. Dielectric masking materials 1, 2, and 3 are used to change a depth for implanting ions 5 in accordance with a shape of a dielectric masking layer, and the buried oxide layer is formed. It is also preferable to form an inclined mask to release stress and to provide a continuous oxide thin film.

公开(公告)号：JP2002043581A

公开(公告)日：2002-02-08

申请号：JP2001154502

申请日：2001-05-23

Applicant: IBM

Inventor： JAMES W ADKISSON ,  PAUL D ANGELO ,  BALLANTINE ARNE W ,  CHRISTOPHER S PUTNAM ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual/wrap-around gate field effect transistor particularly having a short gage length, a low off current and good performance and a method for manufacturing the same. SOLUTION: In the field effect transistor comprising gates each having a length of 10 nm or less and a conductive channel having a width maintained at 1/2 to 1/4 of the length of the gate so that the gates are disposed at least at two sides of the channel, a device having a complete depletion layer is formed without considering the off current. The above-mentioned channel is obtained by forming a groove in a minimum lithographic size, forming sidewalls in the groove and etching a gate structure in a self-alignment manner with the sidewalls. The channel is thereafter epitaxially grown from a source structure in the groove so that the source, the channel and a drain region are integrated in a single crystal structure.

公开(公告)号：SG97204A1

公开(公告)日：2003-07-18

申请号：SG200106328

申请日：2001-10-12

Applicant: IBM

Inventor： JAMES W ADKISSON ,  PAUL D AGNELLO ,  ARNE W BALLANTINE ,  RAMA DIVAKARUNI ,  ERIN JONES ,  EDWARD JOSEPH NOWAK ,  JED H RANKIN

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：SG108827A1

公开(公告)日：2005-02-28

申请号：SG200106036

申请日：2001-10-01

Applicant: IBM

Inventor： JAMES W ADKISSON ,  RAMACHANDRA DIVAKARUNI ,  JEFFREY PETER GAMBINO ,  JACK ALLAN MANDELMAN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L23/538

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions (24) and logic devices are formed in silicon-on-insulator ("SOI") regions (26) and where buried, doped glass to smooth the 250 nm step at the edge of the DRAM array region, making it easier to perform the lithography used to pattern the deep trenches (32) for storage in the bulk region. The resulting structure is also disclosed.