公开(公告)号：US3825902A

公开(公告)日：1974-07-23

申请号：US35601473

申请日：1973-04-30

Applicant: IBM

Inventor： BROWN W ,  DAVIS M ,  PIPITONE R

IPC: G06F9/48 ,  G06F9/46 ,  G06F9/18

CPC classification number: G06F9/461

Abstract: A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.

Abstract translation: 数据处理器具有多组硬件，每组硬件能够自主地控制公共存储器和公共逻辑控制电路来执行程序。 硬件组被分配优先级，优先用于处理中断服务请求。 通过较高优先级输入请求处理中断的任何硬件组保留其处理状态，并且当共同元素的控制返回给它时恢复处理。 包括用于寻址与不同于当前级别的优先级相关联的设备的装置，以便可以为另一任务抢占该不同的级别。 可以检测到抢占级别的中断程序的存在，并且在完成抢占程序之后存储用于恢复的关键状态。

公开(公告)号：BR7403530D0

公开(公告)日：1974-11-19

申请号：BR353074

申请日：1974-04-30

Applicant: IBM

Inventor： PIPITONE R ,  BROWN W ,  DAVIS M

IPC: G06F9/48 ,  G06F9/46 ,  G06F9/06 ,  G05B19/00

Abstract: A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.