Interlevel communication in multilevel priority interrupt system
    1.
    发明授权
    Interlevel communication in multilevel priority interrupt system 失效
    多重优先中断系统中的交互通信

    公开(公告)号:US3825902A

    公开(公告)日:1974-07-23

    申请号:US35601473

    申请日:1973-04-30

    Applicant: IBM

    CPC classification number: G06F9/461

    Abstract: A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.

    Abstract translation: 数据处理器具有多组硬件,每组硬件能够自主地控制公共存储器和公共逻辑控制电路来执行程序。 硬件组被分配优先级,优先用于处理中断服务请求。 通过较高优先级输入请求处理中断的任何硬件组保留其处理状态,并且当共同元素的控制返回给它时恢复处理。 包括用于寻址与不同于当前级别的优先级相关联的设备的装置,以便可以为另一任务抢占该不同的级别。 可以检测到抢占级别的中断程序的存在,并且在完成抢占程序之后存储用于恢复的关键状态。

    Automatic switching of storage protect keys
    2.
    发明授权
    Automatic switching of storage protect keys 失效
    存储保护卡的自动切换

    公开(公告)号:US3825903A

    公开(公告)日:1974-07-23

    申请号:US35601573

    申请日:1973-04-30

    Applicant: IBM

    Inventor: BROWN W

    CPC classification number: G06F12/1466

    Abstract: Storage protect keys are placed in a register in correlation to blocks of main storage. Initialization of a problem program is accompanied by selection of one of these registers via the high order bits of the first instruction to be executed. The key is stored in a separate store and thereafter compared against the key retrieved from the register addressed by the high order bits of each subsequent instruction. Failure to compare indicates a storage boundary has been crossed and an unauthorized instruction execution is being attempted.

    Abstract translation: 存储保护密钥与主存储块相关地放置在寄存器中。 问题程序的初始化伴随着通过要执行的第一指令的高位来选择这些寄存器之一。 密钥存储在单独的存储中,然后与从每个后续指令的高位比特寻址的寄存器中检索的密钥进行比较。 未比较表示存储边界已经越过,并且正在尝试未授权的指令执行。

    4.
    发明专利
    未知

    公开(公告)号:BR7403530D0

    公开(公告)日:1974-11-19

    申请号:BR353074

    申请日:1974-04-30

    Applicant: IBM

    Abstract: A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.

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