Abstract:
A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.
Abstract:
Storage protect keys are placed in a register in correlation to blocks of main storage. Initialization of a problem program is accompanied by selection of one of these registers via the high order bits of the first instruction to be executed. The key is stored in a separate store and thereafter compared against the key retrieved from the register addressed by the high order bits of each subsequent instruction. Failure to compare indicates a storage boundary has been crossed and an unauthorized instruction execution is being attempted.
Abstract:
A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.