公开(公告)号：CA1014666A

公开(公告)日：1977-07-26

申请号：CA197463

申请日：1974-04-11

Applicant: IBM

Inventor： BROWN WENDELL W ,  DAVIS MICHAEL I ,  PIPITONE RALPH M

IPC: G06F9/48 ,  G06F9/46

Abstract: A data processor has multiple sets of hardware each of which is capable of autonomously controlling a common storage and common logical control circuits to execute a program. The hardware sets are allocated priority levels and are preferentially employed for handling interrupt service requests. Any hardware set which is interrupted in processing by a higher priority input request retains its processing status and resumes processing when control of the common elements is returned to it. Apparatus is included for addressing the set associated with a different priority level than the current level so that this different level can be preempted for another task. The presence of an interrupted program in the preempted level can be detected and its critical status stored for restoration after completion of the preempting program.

公开(公告)号：CA2152984A1

公开(公告)日：1996-01-30

申请号：CA2152984

申请日：1995-06-29

Applicant: IBM

Inventor： MENDELSON RICHARD N ,  PIPITONE RALPH M

IPC: G06F13/12 ,  G06F9/46 ,  G06F13/28 ,  H04N7/26 ,  H04N7/50 ,  H04N21/2368 ,  H04N21/434 ,  G06F13/368

Abstract: A data handling arrangement for a computer system, with particular application to multimedia systems, allows device adapters (control units) attached to the system to autonomously (without interrupting the system processor) control processing of a data stream of arbitrary length through memory buffers which are smaller than the stream. In this (stream processing) operation, data constituting the data stream flows through devices controlled by the adapter in succession, and is held in shared memory buffers as it passes between devices. The adapters are prepared for the stream processing operation by a system processor, indicate their preparation status to the processor, receive an initiating signal from the processor, and then proceed to direct the operation to completion without further assistance from the processor. In the operation, the adapters coordinate usage of the memory buffers by respective devices. Coordination is accomplished using a notification signalling protocol defined during preparation of the adapters. For notifying each other of buffer events (filling, emptying, etc.), the adapters use a peer communication feature of a system channel which connects the adapters and devices to the system processor and memory. This feature permits one adapter to directly communicate "notification" information to another control unit without involving the system processor. Information furnished to the adapters during their preparation includes descriptors defining the memory buffers and the notification protocol. It also may include descriptors enabling a control unit to synchronize the processing of data in a stream with events external to the stream; e.g. an external timer function or events associated with the processing of another data stream. Thus, for instance, video and audio components of a live motion picture presentation could be synchronized. The controlling functions affecting stream processing are isolated from the controlled devices, and the processing functions performed by each device on data in a stream are performed independent of the functions performed by any other device relative to the same stream; thereby simplifying development of new devices and new processing functions.