公开(公告)号：CO4700362A1

公开(公告)日：1998-12-29

申请号：CO92323128

申请日：1990-06-01

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  SAMMY D DODDS ,  DHRUVKUMAR M DESAI ,  MANDESE ERNEST N ,  MC NEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/00 ,  G06F13/12

Abstract: En un sistema procesador de datos que incluye un sistemacentral, y al menos un subsistema que puede llevar dispositivos unidos a él, la combinación que comprende: una interfase de órdenes para transferir información entre el sistema central y dicho un subsistema, incluyendo dicha interfase de órdenes: una primera puerta para recibir una orden directa o una orden indirecta desde dicho sistema central, las cuales órdenes son indicativas del tipo de operación que ha de realizarse en dicho subsistema o en los dispositivos unidos a él; y una segunda puerta para recibir desde dicho sistema central un código indicativo de cual dichas ordenes directa o indirecta se recibe en dicha primera puerta, y siendo también indicativo de cual de dicho un subsistema o de un dispositivo unido a él, ha de ejecutar la orden recibida en dicha primera puerta". En un sistema computador que incluye un procesador central que tiene una memoria del sistema, y al menos un subsistema inteligente que puede tener dispositivos unidos a él, la combinación que comprende: una interfase de órdenes incluida en cada uno de tales subsistemas para transferir información entre dicho procesador central y dicho un subsistema inteligente, incluyendo dicha interfase de órdenes:una puerta de interfase de órdenes para recibir una orden directa o una orden indirecta proveniente de dicho procesador central, las cuales ordenes son indicativas del tipo de operación que ha de realizarse por el subsistema inteligente o los dispositivos unidos a él; yuna puerta de atención, para recibir desde dicho procesador central, un código que tenga una primera porción que es indicativa de cual de dichas órdenes directas o de dichas ordenes indirectas se recibe en dicha puerta de interfase de órdenes; y una segunda porción que es indicativa de cual de los sistemas inteligentes o de los dispositivos unidos a él ha de ejecutar la orden recibida en dicha puerta de interfase de órdenes".

公开(公告)号：IN177967B

公开(公告)日：1997-03-01

申请号：IN613DE1990

申请日：1990-06-21

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  MENDELSON RICHARD N ,  HEATH CHESTER A ,  MANDESE ERNEST N

IPC: G06B29/00

公开(公告)号：CA2012400A1

公开(公告)日：1990-12-09

申请号：CA2012400

申请日：1990-03-16

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DODDS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：CA2152984A1

公开(公告)日：1996-01-30

申请号：CA2152984

申请日：1995-06-29

Applicant: IBM

Inventor： MENDELSON RICHARD N ,  PIPITONE RALPH M

IPC: G06F13/12 ,  G06F9/46 ,  G06F13/28 ,  H04N7/26 ,  H04N7/50 ,  H04N21/2368 ,  H04N21/434 ,  G06F13/368

Abstract: A data handling arrangement for a computer system, with particular application to multimedia systems, allows device adapters (control units) attached to the system to autonomously (without interrupting the system processor) control processing of a data stream of arbitrary length through memory buffers which are smaller than the stream. In this (stream processing) operation, data constituting the data stream flows through devices controlled by the adapter in succession, and is held in shared memory buffers as it passes between devices. The adapters are prepared for the stream processing operation by a system processor, indicate their preparation status to the processor, receive an initiating signal from the processor, and then proceed to direct the operation to completion without further assistance from the processor. In the operation, the adapters coordinate usage of the memory buffers by respective devices. Coordination is accomplished using a notification signalling protocol defined during preparation of the adapters. For notifying each other of buffer events (filling, emptying, etc.), the adapters use a peer communication feature of a system channel which connects the adapters and devices to the system processor and memory. This feature permits one adapter to directly communicate "notification" information to another control unit without involving the system processor. Information furnished to the adapters during their preparation includes descriptors defining the memory buffers and the notification protocol. It also may include descriptors enabling a control unit to synchronize the processing of data in a stream with events external to the stream; e.g. an external timer function or events associated with the processing of another data stream. Thus, for instance, video and audio components of a live motion picture presentation could be synchronized. The controlling functions affecting stream processing are isolated from the controlled devices, and the processing functions performed by each device on data in a stream are performed independent of the functions performed by any other device relative to the same stream; thereby simplifying development of new devices and new processing functions.

公开(公告)号：CA1128209A

公开(公告)日：1982-07-20

申请号：CA337648

申请日：1979-10-15

Applicant: IBM

Inventor： BOURKE DONALL G ,  MENDELSON RICHARD N ,  MADRUGA LUIS

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F3/02

Abstract: DATA PROCESSOR INPUT/OUTPUT CONTROLLER An I/O controller is provided for transferring data between a host processor and a plurality of I/O devices wherein the host processor generates a transfer command and each of the plurality of I/O devices generates multiple asynchronous service requests for transfer to the host processor. Control circuitry is provided for controlling the transfer of the service request from the plurality of I/O devices to the host processor. The control circuitry generates a host processor interrupt signal for application to the host processor, such that in response to the host processor interrupt signal, the host processor generates the transfer command to allow the control circuitry to transfer the service request to the host processor.

公开(公告)号：BR9002710A

公开(公告)日：1991-08-20

申请号：BR9002710

申请日：1990-06-08

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DODDS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12 ,  G06F15/20 ,  G06F13/00

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：CA1218158A

公开(公告)日：1987-02-17

申请号：CA417836

申请日：1982-12-15

Applicant: IBM

Inventor： MENDELSON RICHARD N ,  O'NEAL DOUGLAS M ,  SHARP LEO A JR

IPC: G06F13/38 ,  G06F13/12 ,  G06F13/28 ,  G06F13/20 ,  H03M9/00

Abstract: There is disclosed apparatus and a method for extending a parallel channel of the host processor over a serial link to a remote peripheral device. The apparatus includes a microprocessor within I/O channel extension logic which responds to either instructions or data from a host processor. The instructions are of the type commanding the I/O device to perform a specific operation and the data is provided in response to requests for data from the I/O device. The channel extension logic is coupled to the host processor's channel and thus is able to obtain data from the host storage by cycle steal techniques. Within the channel extension logic are means to serialize the information and transmit it in a serial manner over the link. The microprocessor within the channel extension logic creates a frame, including a control byte, which identifies the type of information followed by the data, which frame is then communicated over the serial link to the I/O device. The I/O device also includes a microprocessor and associated logic which responds to the frames communicated by the channel extension logic and generates a frame consisting of a control byte identifying the information type and associated data which is then communicated back over the serial link to the channel extension logic to request action by the channel extension logic or indicate completion of the operation. The I/O device may, for instance, request data be obtained from or stored in the host memory by cycle steal techniques and thereby utilize the features of the host and host channel despite only being coupled thereto by a serial link.

公开(公告)号：PH31356A

公开(公告)日：1998-07-31

申请号：PH40473

申请日：1990-05-03

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DOODS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12 ,  G06F13/24

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：DE2964318D1

公开(公告)日：1983-01-20

申请号：DE2964318

申请日：1979-12-04

Applicant: IBM

Inventor： BOURKE DONALL G ,  MENDELSON RICHARD N ,  MADRUGA LUIS

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F3/04