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    DENSE DUAL-PLANE DEVICES
    1.
    发明公开
    DENSE DUAL-PLANE DEVICES 有权
    密度双层设备

    公开(公告)号：EP1573823A4

    公开(公告)日：2009-03-25

    申请号：EP03790326

    申请日：2003-12-05

    Applicant: IBM

    Inventor： NOWAK EDWARD J ,  RAINEY BETHANN

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

    CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An MOS device with first and second freestanding semiconductor bodies (40N, 40P) formed on a substrate (10). The first freestanding semiconductor body (40N or 40P) has a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body (40P or 40N). These portions of said first and second freestanding semiconductor bodies (40N, 40P) have respective first and second crystalline orientations. A first gate electrode (60) crosses over at least part of said first portion of said first freestanding semiconductor body (40N or 40P) at a non-orthogonal angle, as does a second gate electrode (60) over the first portion of the second freestanding semiconductor body (40P or 40N).

    VIRTUAL BODY-CONTACTED TRIGATE
    3.
    发明公开
    VIRTUAL BODY-CONTACTED TRIGATE 审中-公开
    VIRTUELLESKÖRPERKONTAKTIERTESTRIGATE

    公开(公告)号：EP1908111A4

    公开(公告)日：2008-09-03

    申请号：EP06788064

    申请日：2006-07-21

    Applicant: IBM

    Inventor： ANDERSON BRENT A ,  BREITWISCH MATTHEW J ,  NOWAK EDWARD J ,  RAINEY BETHANN

    IPC: H01L29/12 ,  H01L21/84

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

    Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate (101 ); a silicon germanium (SiGe) layer (103) over the substrate (103); a semiconductor layer (105) over and adjacent to the SiGe layer (103); an insulating layer (109a) adjacent to the substrate (101), the SiGe layer (103), and the semiconductor layer (105); a pair of first gate structures (111) adjacent to the insulating layer (1 09a); and a second gate structure (113) over the insulating layer (109a). Preferably, the insulating layer (109a) is adjacent to a side surface of the SiGe layer (103) and an upper surface of the semiconductor layer (105), a lower surface of the semiconductor layer (105), and a side surface of the semiconductor layer (105). Preferably, the SiGe layer (103) comprises carbon. Preferably, the pair of first gate structures (111) are substantially transverse to the second gate structure (113). Additionally, the pair of first gate structures (111) are preferably encapsulated by the insulating layer (109a).

    Abstract translation: 一种场效应晶体管（FET）及其形成方法，包括衬底（101）; 在衬底（103）上的硅锗（SiGe）层（103）; 在所述SiGe层（103）上方并且与所述SiGe层（103）相邻的半导体层（105）; 与衬底（101），SiGe层（103）和半导体层（105）相邻的绝缘层（109a）; 一对第一栅极结构（111），与绝缘层（109a）相邻; 和在绝缘层（109a）上的第二栅极结构（113）。 优选地，绝缘层（109a）与SiGe层（103）的侧表面和半导体层（105）的上表面，半导体层（105）的下表面以及半导体层 半导体层（105）。 优选地，SiGe层（103）包含碳。 优选地，该对第一栅极结构（111）基本上横向于第二栅极结构（113）。 此外，一对第一栅极结构（111）优选由绝缘层（109a）封装。

    METHODS OF FORMING STRUCTURE AND SPACER AND RELATED FINFET
    4.
    发明公开
    METHODS OF FORMING STRUCTURE AND SPACER AND RELATED FINFET 审中-公开
    及其形成方法的结构的距离元件及相关的FinFET

    公开(公告)号：EP1573804A4

    公开(公告)日：2006-03-08

    申请号：EP02798557

    申请日：2002-12-19

    Applicant: IBM

    Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETHANN

    IPC: H01L21/84 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66795

    Abstract: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124) , and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.

    VIRTUAL BODY-CONTACTED TRIGATE
    7.
    发明申请
    VIRTUAL BODY-CONTACTED TRIGATE 审中-公开
    虚拟身体接触的TRIGATE

    公开(公告)号：WO2007015957A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2006028312

    申请日：2006-07-21

    Applicant: IBM ,  ANDERSON BRENT A ,  BREITWISCH MATTHEW J ,  NOWAK EDWARD J ,  RAINEY BETHANN

    Inventor： ANDERSON BRENT A ,  BREITWISCH MATTHEW J ,  NOWAK EDWARD J ,  RAINEY BETHANN

    IPC: H01L29/12 ,  H01L21/84

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

    Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate (101 ); a silicon germanium (SiGe) layer (103) over the substrate (103); a semiconductor layer (105) over and adjacent to the SiGe layer (103); an insulating layer (109a) adjacent to the substrate (101), the SiGe layer (103), and the semiconductor layer (105); a pair of first gate structures (111) adjacent to the insulating layer (1 09a); and a second gate structure (113) over the insulating layer (109a). Preferably, the insulating layer (109a) is adjacent to a side surface of the SiGe layer (103) and an upper surface of the semiconductor layer (105), a lower surface of the semiconductor layer (105), and a side surface of the semiconductor layer (105). Preferably, the SiGe layer (103) comprises carbon. Preferably, the pair of first gate structures (111) are substantially transverse to the second gate structure (113). Additionally, the pair of first gate structures (111) are preferably encapsulated by the insulating layer (109a).

    Abstract translation: 场效应晶体管（FET）和形成FET的方法包括：衬底（101）; 在所述衬底（103）上方的硅锗（SiGe）层（103）; 在所述SiGe层（103）上并邻近所述半导体层（105）; 与基板（101）相邻的绝缘层（109a），SiGe层（103）和半导体层（105）; 与绝缘层（109a）相邻的一对第一栅极结构（111）; 和绝缘层（109a）上的第二栅极结构（113）。 优选地，绝缘层（109a）与SiGe层（103）的侧表面和半导体层（105）的上表面，半导体层（105）的下表面和 半导体层（105）。 优选地，SiGe层（103）包含碳。 优选地，一对第一栅极结构（111）基本上横向于第二栅极结构（113）。 另外，一对第一栅极结构（111）优选地被绝缘层（109a）封装。

    METHOD OF FORMING FREESTANDING SEMICONDUCTOR LAYER
    8.
    发明申请
    METHOD OF FORMING FREESTANDING SEMICONDUCTOR LAYER 审中-公开
    形成半导体层的方法

    公开(公告)号：WO2005001904A3

    公开(公告)日：2005-09-01

    申请号：PCT/US2004020552

    申请日：2004-06-25

    Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RAINEY BETHANN

    Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RAINEY BETHANN

    IPC: H01L20060101 ,  H01L21/20 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/036

    CPC classification number: H01L29/785 ,  H01L21/2022 ,  H01L29/66795

    Abstract: A method of providing a freestanding semiconductor layer (26) on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel (22) on a monocrystalline base structure (20). A conformal polycrystalline semiconductor layer (24) is then formed on the mandrel (22) and on the base structure (20), wherein the polycrystalline layer (24) contacts the base structure (20). The polycrystalline semiconductor layer (24) is then recrystallized so that it has a crystallinity substantially similar to that of the base structure (20). Thus, a freestanding semiconductor layer (26) is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

    Abstract translation: 在常规SOI或体硅衬底硅器件上提供独立半导体层（26）的方法包括在单晶基底结构（20）上形成非晶或多晶心轴（22）。 然后在心轴（22）和基底结构（20）上形成共形多晶半导体层（24），其中多晶层（24）接触基底结构（20）。 然后将多晶半导体层（24）重结晶，使其具有与基底结构（20）基本上相似的结晶度。 因此，独立式半导体层（26）以其厚度和高度的高度控制并且保持厚度均匀性形成。

    DENSE DUAL-PLANE DEVICES
    9.
    发明专利
    DENSE DUAL-PLANE DEVICES 未知

    公开(公告)号：AU2003293380A1

    公开(公告)日：2004-07-29

    申请号：AU2003293380

    申请日：2003-12-05

    Applicant: IBM

    Inventor： NOWAK EDWARD J ,  RAINEY BETHANN

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

    Abstract: A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body. These portions of said first and second freestanding semiconductor bodies have respective first and second crystalline orientations. A first gate electrode crosses over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle, as does a second gate electrode over the first portion of the second freestanding semiconductor body.

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