公开(公告)号：JPS62106545A

公开(公告)日：1987-05-18

申请号：JP23023886

申请日：1986-09-30

Applicant: IBM

Inventor： EMMA PHILIP G ,  POMERENE JAMES H ,  RAO GURURAJ S ,  RECHTSCHAFFEN RUDOLPH N ,  SACHAR HOWARD E ,  SPARACIO FRANK J

IPC: G06F9/38

公开(公告)号：CA1238984A

公开(公告)日：1988-07-05

申请号：CA494698

申请日：1985-11-06

Applicant: IBM

Inventor： POMERENE JAMES H ,  PUZAK THOMAS R ,  RECHTSCHAFFEN RUDOLPH N ,  SO KIMMING

IPC: G06F12/08

Abstract: A COOPERATIVE MEMORY HIERARCHY A prefetching mechanism for a memory hierarchy which includes at least two levels of storage, with L1 being a high-speed low-capacity memory, and L2 being a low-speed high-capacity memory, with the units of L2 and L1 being blocks and sub-blocks respectively, with each block containing several sub-blocks in consecutive addresses. Each sub-block is provided an additional bit, called a r-bit, which indicates that the sub-block has been previously stored in L1 when the bit is 1, and has not been previously stored in L1 when the bit is 0. Initially when a block is loaded into L2 each of the r-bits in the sub-block are set to 0. When a sub-block is transferred from L1 to L2, its r-bit is then set to 1 in the L2 block, to indicate its previous storage in L1. When the CPU references a given sub-block which is not present in L1, and has to be fetched from L2 to L1, the remaining sub-blocks in this block having r-bits set to 1 are prefetched to L1. This prefetching of the other sub-blocks having r-bits set to 1 results in a more efficient utilization of the L1 storage capacity and results in a higher hit ratio.

公开(公告)号：CA1268555A

公开(公告)日：1990-05-01

申请号：CA529483

申请日：1987-02-11

Applicant: IBM

Inventor： EMMA PHILIP G ,  POMERENE JAMES H ,  PUZAK THOMAS R ,  RECHTSCHAFFEN RUDOLPH N ,  SPARACIO FRANK J

IPC: G06F9/38

Abstract: BRANCH STREAM COPROCESSOR A novel approach to reducing delays resulting from resolution of conditional branch instructions, in which such instructions are pre-executed in a coprocessor which precedes a pipeline processor and prepares an instruction stream for input to the pipeline processor. Because of this pre-execution, the input instruction stream has fewer conditional branches for the pipeline processor to resolve. Also, the coprocessor may handle address generation interlock situations which also cause execution delays in the pipeline processor.

公开(公告)号：DE3687744D1

公开(公告)日：1993-03-25

申请号：DE3687744

申请日：1986-09-05

Applicant: IBM

Inventor： EMMA PHILIP G ,  POMERENE JAMES H ,  RAO GURURAJ S ,  RECHTSCHAFFEN RUDOLPH N ,  SACHAR HOWARD E ,  SPARACIO FRANK J

IPC: G06F9/38

Abstract: A data-dependent branch table (64) is described, which is a mechanism that is sensitive to those operands that will be tested in order to determine branch action outcomes. The data dependent branch table operates in conjunction with a branch history table to anticipate those instances where the branch history table will make an erroneous prediction, including means to correct the branch history table prior to the time that the actual prediction is made.

公开(公告)号：DE3687744T2

公开(公告)日：1993-08-19

申请号：DE3687744

申请日：1986-09-05

Applicant: IBM

Inventor： EMMA PHILIP G ,  POMERENE JAMES H ,  RAO GURURAJ S ,  RECHTSCHAFFEN RUDOLPH N ,  SACHAR HOWARD E ,  SPARACIO FRANK J

IPC: G06F9/38

Abstract: A data-dependent branch table (64) is described, which is a mechanism that is sensitive to those operands that will be tested in order to determine branch action outcomes. The data dependent branch table operates in conjunction with a branch history table to anticipate those instances where the branch history table will make an erroneous prediction, including means to correct the branch history table prior to the time that the actual prediction is made.

公开(公告)号：CA1244554A

公开(公告)日：1988-11-08

申请号：CA502802

申请日：1986-02-26

Applicant: IBM

Inventor： POMERENE JAMES H ,  PUZAK THOMAS R ,  RECHTSCHAFFEN RUDOLPH N ,  ROSENFELD PHILIP L ,  SPARACIO FRANK J

IPC: G06F9/38

Abstract: PAGEABLE BRANCH HISTORY TABLE A branch history table (BHT) is substantially improved by dividing it into two parts: an active area, and a backup area. The active area contains entries for a small number of branches which the processor can encounter in the near future and the backup area contains all other branch entries. Means are provided to bring entries from the backup area into the active area ahead of when the processor will use those entries. When entries are no longer needed they are removed from the active area and put into the backup area if not already there. New entries for the near future are brought in, so that the active area, though small, will almost always contain the branch information needed by the processor. The small size of the active area allows it to be fast and to be optimally located in the processor layout. The backup area can be located outside the critical part of the layout and can therefore be made larger than would be practicable for a standard BHT.