公开(公告)号：WO2004049527A3

公开(公告)日：2004-10-28

申请号：PCT/EP0313343

申请日：2003-10-23

Applicant: IBM ,  IBM FRANCE

Inventor： BOZSO FERENC M ,  EMMA PHILIP G

IPC: H01S5/026 ,  H01S5/042 ,  H01S5/062 ,  H01S5/183 ,  H01S5/022

CPC classification number: H01S5/0428 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/12032 ,  H01L2924/15192 ,  H01S5/02248 ,  H01S5/06226 ,  H01S5/183 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A high speed optical channel including an optical driver (334) and a photodetector (338) in a CMOS photoreceiver (338). The optical channel driver includes a FET driver circuit (334) driving a passive element (110) (e.g., an integrated loop inductor) and a vertical cavity surface emitting laser (VCSEL) diode (312). The VCSEL diode is biased by a bias supply. The integrated loop inductor (110) may be integrated in CMOS technology and on the same IC chip as either/both of the FET driver and the VCSEL diode. The photodetector (338) is in a semiconductor (silicon) layer that may be on an insulator layer, i.e., SOI. One or more ultrathin metal electrodes (M)

Abstract translation: 一种在CMOS光接收器（338）中包括光驱动器（334）和光电检测器（338）的高速光通道。 光通道驱动器包括驱动无源元件（110）（例如，集成环路电感器）和垂直腔表面发射激光器（VCSEL）二极管（312）的FET驱动器电路（334）。 VCSEL二极管由偏置电源偏置。 集成环路电感器（110）可以集成在CMOS技术中，并且与FET驱动器和VCSEL二极管中的一个/两者集成在同一IC芯片上。 光电检测器（338）位于可以在绝缘体层（即SOI）上的半导体（硅）层中。 在硅层上的一个或多个超薄金属电极（M）<< 2000A）形成肖特基势垒二极管结，该结二极管结又形成了在超薄金属电极（M）和 肖特基势垒二极管结。

公开(公告)号：JP2004334872A

公开(公告)日：2004-11-25

申请号：JP2004135680

申请日：2004-04-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOSE PRADIP ,  BROOKS DAVID M ,  COOK PETER W ,  EMMA PHILIP G ,  GSCHWIND MICHAEL K ,  SCHUSTER STANLEY E ,  SRINIVASAN VIJAYALAKSHMI

IPC: G06F1/32 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption of a processor without tolerating the loss in performance and reduce leak power of the processor. SOLUTION: An integrated circuit device (IC) comprises a unit power adjusting mechanism, a leak reduction circuit which reduces LdI/de noise in the integrated circuit device to adjustably reduce leak power, and an activity prediction unit 130 which calls active/dormant states in the IC. The activity prediction unit 130 determines turn-on and turn-off times for IC unit. The activity prediction unit 130 controls a supply voltage selection circuit, selectively pass the supply voltage to a supply line at predicted turn-on time, and selectively inhibits the supply voltage at predicted turn-off time. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JPS62106545A

公开(公告)日：1987-05-18

申请号：JP23023886

申请日：1986-09-30

Applicant: IBM

Inventor： EMMA PHILIP G ,  POMERENE JAMES H ,  RAO GURURAJ S ,  RECHTSCHAFFEN RUDOLPH N ,  SACHAR HOWARD E ,  SPARACIO FRANK J

IPC: G06F9/38

公开(公告)号：JP2004177963A

公开(公告)日：2004-06-24

申请号：JP2003396197

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOZSO FERENC M ,  EMMA PHILIP G

IPC: H05K1/14 ,  G02B6/12 ,  G02B6/122 ,  G02B6/124 ,  G02B6/38 ,  G02B6/42 ,  G02B6/43 ,  H05K1/02

CPC classification number: G02B6/43 ,  G02B6/12004 ,  G02B6/124 ,  G02B6/3885 ,  G02B6/4246 ,  G02B6/4292 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0274 ,  H05K1/14 ,  H05K2201/044

Abstract: PROBLEM TO BE SOLVED: To improve system communication and to improve on-board communication. SOLUTION: An optically connectable circuit board and optical components mounted thereon are provided. At least one of components includes a light tranceiver 405 and provides an optical connection to the board 401. Electronic components may be directly connected to the board electrically or optically. some electronic components may be optically and indirectly connected to the board 401 via the intermediate optical components. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004177962A

公开(公告)日：2004-06-24

申请号：JP2003396178

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOZSO FERENC M ,  EMMA PHILIP G

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/36 ,  G02B6/43 ,  G06F13/40 ,  H04B10/12 ,  H04B10/13 ,  H04B10/135 ,  H04B10/14

CPC classification number: G06F13/409 ,  G02B6/43

Abstract: PROBLEM TO BE SOLVED: To improve system communications and to improve on-board communications. SOLUTION: This invention relates to an electronic system provided with components communicating over optical channels, a board initialization and continuity check, and a method of transferring data over the optical channels. The system includes a backplane 403 provided with board 401 to board 401 signal wiring and a shared optical bus. Optical gratings are attached to the backplane and to circuit boards to pass optical energy between an optical transceiver 405 and board/backplane. The optical transceiver at each end of each optical jumper relays optical signals between the optical jumper and the connected circuit board or the backplane. The optical jumpers optically connect the circuit boards to the backplane. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004139041A

公开(公告)日：2004-05-13

申请号：JP2003313303

申请日：2003-09-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHRISTOPH BERGER ,  KNICKERBOCKER JOHN U ,  EMMA PHILIP G ,  DECUSATIS CASIMER M ,  BROOKS CAMERON ,  JACOBOWITZ LAWRENCE

IPC: G02B6/10 ,  G02B6/122 ,  G02B6/28 ,  G02B6/30 ,  G02B6/34 ,  G02B6/38 ,  G02B6/43 ,  H04B10/02 ,  H04B10/12

CPC classification number: G02B6/30 ,  G02B6/2826 ,  G02B6/3817 ,  G02B6/3829 ,  G02B6/3839 ,  G02B6/43

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for forming a step-like construction for connection of optical waveguides between a card and a backplane. SOLUTION: Optical waveguides 20 and conductors are embedded in a card 10, and ends 45 terminating at the step-like construction exist therein. Optical fiber ribbons 50 project from the ends 45. Also, a guide structure 60 is connected to the ends 45. The guide structure 60 has grooves for guiding and aligning the ribbons 50. Optical waveguides 25 and conductors are embedded in a backplane 70 as well, and have ends 75 terminating at the step-like construction and an aperture 90 having a slope. A guide structure 80 is connected to the ends 75. The aperture 90 having the slope accepts and guides the ribbons 50 and brings the ribbons into tight proximity to the optical waveguides 25, thereby forming the step-like construction consisting of the connected waveguides between the card 10 and the backplane 70. COPYRIGHT: (C)2004,JPO

公开(公告)号：GB2494328B

公开(公告)日：2014-11-05

申请号：GB201221491

申请日：2011-04-27

Applicant: IBM

Inventor： EMMA PHILIP G ,  KURSUN EREN ,  RIVERS JUDE A

IPC: H01L23/49 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

公开(公告)号：CA1268555A

公开(公告)日：1990-05-01

申请号：CA529483

申请日：1987-02-11

Applicant: IBM

Inventor： EMMA PHILIP G ,  POMERENE JAMES H ,  PUZAK THOMAS R ,  RECHTSCHAFFEN RUDOLPH N ,  SPARACIO FRANK J

IPC: G06F9/38

Abstract: BRANCH STREAM COPROCESSOR A novel approach to reducing delays resulting from resolution of conditional branch instructions, in which such instructions are pre-executed in a coprocessor which precedes a pipeline processor and prepares an instruction stream for input to the pipeline processor. Because of this pre-execution, the input instruction stream has fewer conditional branches for the pipeline processor to resolve. Also, the coprocessor may handle address generation interlock situations which also cause execution delays in the pipeline processor.

公开(公告)号：GB2494328A

公开(公告)日：2013-03-06

申请号：GB201221491

申请日：2011-04-27

Applicant: IBM

Inventor： EMMA PHILIP G ,  KURSUN EREN ,  RIVERS JUDE A

IPC: H01L23/49 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

Abstract: Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.

公开(公告)号：AU2003269997A1

公开(公告)日：2005-04-14

申请号：AU2003269997

申请日：2003-08-26

Applicant: COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  IBM ,  BOSE PRADIP ,  CITRON DANIEL M

Inventor： COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  BOSE PRADIP ,  CITRON DANIEL M

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/38

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.