TOGGLE OF DIVISION TRANSACTION MODE OF PCI-X BRIDGE BUFFER

    公开(公告)号:JP2001005774A

    公开(公告)日:2001-01-12

    申请号:JP2000139269

    申请日:2000-05-12

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To improve bus efficiency and total system performance by providing a means which switches and sets a division transaction mode to an overcommit mode when an inter-PCI-X bridge is not overcommitted. SOLUTION: A system 24 provides a toggle for switching the division transaction mode of the bridge 34 between peripheral components interconnect-Xs (PCI-X) between an 'overcomit inhibition' mode and 'overcomit' mode or 'flood' mode when the bridge 34 is not overcommitted. Then the system 24 toggles and switches the division transaction mode of the PCI-X bridge buffer, and then retrial and disconnection are generally minimized by the inter-PCI-X bridge 34 to improve the bus efficiency and total system performance.

    SECONDARY INPUT AND OUTPUT BUS HAVING EXTENSION SLOT CAPABILITY AND HOT PLUGGING FUNCTION

    公开(公告)号:JPH1074177A

    公开(公告)日:1998-03-17

    申请号:JP12513497

    申请日:1997-05-15

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To change a specific adaptor card without reducing the total electric power of a computer system by preparing a single connector slot to accept a card that executes a specific function of an input/output device, a memory, etc. SOLUTION: A PCI bridge chip 203 performs the interrupt processing, the transfer of messages, the arbitration, the snooping, etc. Furthermore, a logic and a function are added to attain the conversion of a bus protocol between a system bus and an input/output bus 202. The bus 202 is connected to at least a driver/receiver module 204 which offers an interface between an actual adaptor slot 206 including a connector and the additional logic and the bus 202. The slot 206 accepts an input/output device 208. In such a constitution, a user can replace a specific adaptor card with another without turning off the system power supply.

    BUS ARBITER WITH REINFORCED FUNCTION USING VARIABLE PRIORITY AND FAIRNESS

    公开(公告)号:JP2001075918A

    公开(公告)日:2001-03-23

    申请号:JP2000228134

    申请日:2000-07-28

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To change arbitration priority levels by making a bus arbiter include logic in which a fairness system is embedded. SOLUTION: When a plurality of devices simultaneously request a bus, this bus arbiter resets all the bits of a fairness register to zero and starts a fairness protocol sequence. The bus arbiter deasserts all currently asserted enabling signals. Then, the bus arbiter asserts an enabling signal to a request source which does not set 1 in a corresponding fairness register bit and has the highest priority. Subsequently, the bus arbiter uses fairness algorithm and asserts an enabling signal to a request source having the highest priority when there is another device to which a request signal is asserted and which sets 1 in a fairness bit.

    METHOD AND SYSTEM FOR SUPPORTING PLURAL PERIPHERAL COMPONENTS INTERCONNECT BUSES SUPPORTING VARIOUS FREQUENCY OPERATIONS

    公开(公告)号:JP2000082035A

    公开(公告)日:2000-03-21

    申请号:JP9602999

    申请日:1999-04-02

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide the method and system for supporting plural peripheral components interconnect(PCI) local buses through a PCI host bridge having PIC interfaces in a data processing system. SOLUTION: By the method and system, a processor 12 and a system memory are connected to a system bus 20. One or plural PIC local buses 22 are connected to the system bus 20 by a single PCI host bridge having a bus/frequency control logic mechanism and a bus clock. The respective PCI local buses 22 include in-line electronic switches which divide the PCI local buses 22 into PCI local bus segments supporting more PCI component slots than specified by the PCI local bus standards.

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