公开(公告)号：JPH11328098A

公开(公告)日：1999-11-30

申请号：JP6004299

申请日：1999-03-08

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  DANNY MARVIN NEIL ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To obtain a method and a system which support a multiple peripheral component interconnection (PCI) bus by a single PCI host bridge in a data processor. SOLUTION: In the method and system, a processor 48 and a system memory 50 are connected to a system bus 20. First and second PCI local busses are connected to the system bus through the PCI host bridge. First and second PCI local busses have plural inline electronic switches to divide the PCI local busses into PCI local bus segments which support plural PCI peripheral component slots. Plural pairs of inline electronic switches are opened and closed based on a bus control logic in the PCI host bridge 76 to provide a maximum of 14 PCI peripheral component slots, so as to access the system bus through the single PCI host bridge 76.

公开(公告)号：JP2000082035A

公开(公告)日：2000-03-21

申请号：JP9602999

申请日：1999-04-02

Applicant: IBM

Inventor： RICHARD ALLEN KELLY ,  DANNY MARVIN NEIL ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To provide the method and system for supporting plural peripheral components interconnect(PCI) local buses through a PCI host bridge having PIC interfaces in a data processing system. SOLUTION: By the method and system, a processor 12 and a system memory are connected to a system bus 20. One or plural PIC local buses 22 are connected to the system bus 20 by a single PCI host bridge having a bus/frequency control logic mechanism and a bus clock. The respective PCI local buses 22 include in-line electronic switches which divide the PCI local buses 22 into PCI local bus segments supporting more PCI component slots than specified by the PCI local bus standards.

公开(公告)号：JP2001005774A

公开(公告)日：2001-01-12

申请号：JP2000139269

申请日：2000-05-12

Applicant: IBM

Inventor： RICHARD ALLEN KELLY ,  DANNY MARVIN NEIL ,  YANES ADALBERTO GUILLERMO

IPC: G06F13/12 ,  G06F13/14 ,  G06F13/16 ,  G06F13/20 ,  G06F13/36 ,  G06F13/364 ,  G06F13/38 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To improve bus efficiency and total system performance by providing a means which switches and sets a division transaction mode to an overcommit mode when an inter-PCI-X bridge is not overcommitted. SOLUTION: A system 24 provides a toggle for switching the division transaction mode of the bridge 34 between peripheral components interconnect-Xs (PCI-X) between an 'overcomit inhibition' mode and 'overcomit' mode or 'flood' mode when the bridge 34 is not overcommitted. Then the system 24 toggles and switches the division transaction mode of the PCI-X bridge buffer, and then retrial and disconnection are generally minimized by the inter-PCI-X bridge 34 to improve the bus efficiency and total system performance.

公开(公告)号：JPH11353267A

公开(公告)日：1999-12-24

申请号：JP11012299

申请日：1999-04-16

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  DANNY MARVIN NEIL ,  THURBER STEVEN MARK

IPC: G06F13/10 ,  G06F9/445 ,  G06F13/14

Abstract: PROBLEM TO BE SOLVED: To provide an improved computer system having an extension bus which can add a peripheral device to the system. SOLUTION: In a method registering newly added peripheral device to a computer system 100, the peripheral device has a response by transmitting a state message to a bus of the system 100 within a prescribed period after the asserting of a reset signal supplied to the peripheral device is released and in response to the access trial given to the peripheral device. Thus, it's possible to evade the stoppage of a function and also to evade the necessity to reboot of the system 100 to initialize a new peripheral device to the system 100. If a a response is generated within an initialization waiting time period shorter than the prescribed period, the peripheral device is allowed to transmit a trial response in an early stage. Furthermore, the peripheral device can respond to a non-configuration cycle right after a configuration is completed. The internal logic of the peripheral device is initialized after responded by a state message.

公开(公告)号：JPH11353244A

公开(公告)日：1999-12-24

申请号：JP11065099

申请日：1999-04-19

Applicant: IBM

Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  DANNY MARVIN NEIL ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

IPC: G06F13/00 ,  G06F11/07

Abstract: PROBLEM TO BE SOLVED: To prevent damage due to a bus error in loading operation or storing operation through the identification of a device which encountered an error before by using forcible illegal data parity or 0-byte enabling. SOLUTION: Device select lines from respective I/O devices 132 and 134 are connected individually to a PCT host bridge 124 and if an error occurs on a PCI(peripheral component interconnect) bus, the device number of the faulty device is recorded in an error register 204. Following loading operation and storing operation are suspended until the error register is reset and until the device number of the object device is checked in the error register. If the object device got out of order before, the completion of the loading/storing operation on the device is stopped by forcing the illegal parity or setting all of byte enabling to zero. The I/O devices activate their device select lines when the illegal parity of 0-byte enabling is forced to answer a load request or store request, but accept no store data.