公开(公告)号：EP0801352A3

公开(公告)日：1998-10-14

申请号：EP97301904

申请日：1997-03-20

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36 ,  G06F13/4027

Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.

Abstract translation: 数据处理系统10包括处理器12，系统存储器15和多个外围设备401,403，以及一个或多个桥接器400，其可以连接处理器，存储器和外围设备以及其他主机或外围设备，诸如 网络。 诸如PCI主桥之类的桥连接在主总线（例如系统总线）14和次总线16之间。主桥400提供双主桥功能，其创建两个次级总线接口。 这允许在一个双主桥下增加加载能力，而在一个正常主桥下允许的插槽数量较少。 还包括用于提供仲裁控制和将交易转向相应总线接口的附加控制逻辑。 此外，还提供了跨两个辅助总线接口的对等支持。

公开(公告)号：JP2009193590A

公开(公告)日：2009-08-27

申请号：JP2009055764

申请日：2009-03-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARNDT RICHARD LOUIS ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F12/14 ,  G06F9/46 ,  G06F13/36 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To provide a method, system, and apparatus for preventing input/output (I/O) used by an operating system (OS) image, in a logically partitioned data processing system, from corrupting or fetching data allocated to another OS image within the system. SOLUTION: This logically partitioned data processing system includes a plurality of logical partitions, the plurality of operating systems (OS), a plurality of memory locations, a plurality of I/O adapters (IOA), and a hypervisor. Each of the operating system images is assigned to each of different logical partitions. Each of the memory locations and each of the input/output adapters are assigned to one of the logical partitions. The hypervisor prevents transmission of data between the input/output adapter in one of the logical partitions and the memory location assigned to the other logical partition during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在逻辑分区的数据处理系统中防止操作系统（OS）图像使用的输入/输出（I / O）的方法，系统和装置，以破坏或获取数据 分配给系统中的另一个OS映像。 解决方案：该逻辑分区数据处理系统包括多个逻辑分区，多个操作系统（OS），多个存储器位置，多个I / O适配器（IOA）和管理程序。 每个操作系统映像被分配给每个不同的逻辑分区。 每个存储器位置和每个输入/输出适配器被分配给一个逻辑分区。 虚拟机管理程序防止在直接存储器访问（DMA）操作期间在逻辑分区之一的输入/输出适配器和分配给另一逻辑分区的存储器位置之间传输数据，通过将每个输入/输出适配器分配给I / O总线DMA地址。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPH11328098A

公开(公告)日：1999-11-30

申请号：JP6004299

申请日：1999-03-08

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  DANNY MARVIN NEIL ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To obtain a method and a system which support a multiple peripheral component interconnection (PCI) bus by a single PCI host bridge in a data processor. SOLUTION: In the method and system, a processor 48 and a system memory 50 are connected to a system bus 20. First and second PCI local busses are connected to the system bus through the PCI host bridge. First and second PCI local busses have plural inline electronic switches to divide the PCI local busses into PCI local bus segments which support plural PCI peripheral component slots. Plural pairs of inline electronic switches are opened and closed based on a bus control logic in the PCI host bridge 76 to provide a maximum of 14 PCI peripheral component slots, so as to access the system bus through the single PCI host bridge 76.

公开(公告)号：JP2002318701A

公开(公告)日：2002-10-31

申请号：JP2002010686

申请日：2002-01-18

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F12/14 ,  G06F9/46 ,  G06F13/36 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To prevent an I/O, which is to be used by one OS within a logically divided system, from destroying or fetching data belonging to the other OS within the system. SOLUTION: A hypervisor assigns an I/O bus direct memory access(DMA) address range to each of input/output adapters and prevents data from being transmitted between the input/output adapter inside one logic domain and a memory location assigned to the other logic domain during DMA operation. The I/O adapter(IOA) is connected through a terminal bridge to a PCI host bridge. A single terminal bridge can support a plurality of IOA as well, every terminal bridge has a plurality of sets of range registers, and each of sets is related to each of IOA. An arbiter is provided for selecting one of input/output adapters to use a PCI bus. The terminal bridge investigates a grant signal from the arbiter to the IOA and the set of range registers to be used is determined.

公开(公告)号：JP2001075918A

公开(公告)日：2001-03-23

申请号：JP2000228134

申请日：2000-07-28

Applicant: IBM

Inventor： RICHARD ALLEN KELLY ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To change arbitration priority levels by making a bus arbiter include logic in which a fairness system is embedded. SOLUTION: When a plurality of devices simultaneously request a bus, this bus arbiter resets all the bits of a fairness register to zero and starts a fairness protocol sequence. The bus arbiter deasserts all currently asserted enabling signals. Then, the bus arbiter asserts an enabling signal to a request source which does not set 1 in a corresponding fairness register bit and has the highest priority. Subsequently, the bus arbiter uses fairness algorithm and asserts an enabling signal to a request source having the highest priority when there is another device to which a request signal is asserted and which sets 1 in a fairness bit.

公开(公告)号：JP2000082035A

公开(公告)日：2000-03-21

申请号：JP9602999

申请日：1999-04-02

Applicant: IBM

Inventor： RICHARD ALLEN KELLY ,  DANNY MARVIN NEIL ,  THURBER STEVE MARK

IPC: G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To provide the method and system for supporting plural peripheral components interconnect(PCI) local buses through a PCI host bridge having PIC interfaces in a data processing system. SOLUTION: By the method and system, a processor 12 and a system memory are connected to a system bus 20. One or plural PIC local buses 22 are connected to the system bus 20 by a single PCI host bridge having a bus/frequency control logic mechanism and a bus clock. The respective PCI local buses 22 include in-line electronic switches which divide the PCI local buses 22 into PCI local bus segments supporting more PCI component slots than specified by the PCI local bus standards.

公开(公告)号：DE69736872T2

公开(公告)日：2007-04-26

申请号：DE69736872

申请日：1997-03-20

Applicant: IBM

Inventor： GUTHRIE GUY LYNN ,  KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVE MARK

IPC: G06F13/40 ,  G06F13/36

Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.

公开(公告)号：JP2008009980A

公开(公告)日：2008-01-17

申请号：JP2007163944

申请日：2007-06-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： THURBER STEVE MARK ,  RICHARD LEWIS ARNT ,  SCHLIPF THOMAS

IPC: G06F13/14 ,  G06F11/18 ,  G06F13/00

CPC classification number: H04L47/10 ,  H04L41/0659 ,  H04L47/11 ,  H04L47/30 ,  H04L47/32 ,  H04L47/39 ,  H04L49/90

Abstract: PROBLEM TO BE SOLVED: To provide a computer implemented method, apparatus and mechanism for recovery of an I/O fabric that becomes terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems.
SOLUTION: Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Storage requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种计算机实现的方法，装置和机制，用于恢复由于导致缓冲器/队列填充的故障而终止拥塞或死锁的I / O结构，从而使根复合体 无法访问其I / O子系统。 解决方案：在检测到最终拥塞或死锁的传输队列时，由队列中的每个项目进行相应的检查和处理，暂停其他根组合对这种队列的访问。 队列中的存储请求和DMA读回应数据包将被丢弃，队列中的加载请求将通过返回特殊的完成包进行处理。 然后恢复根组合对队列的访问。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007287140A

公开(公告)日：2007-11-01

申请号：JP2007098505

申请日：2007-04-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： THURBER STEVE MARK ,  CARL ALFRED BENDER ,  ADARUBERUTO GIRERUMO YANESU ,  PATRICK ALLEN BATSUKURANDO

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F12/1081

Abstract: PROBLEM TO BE SOLVED: To provide a mechanism for temporarily stopping DMA operation selected in a physical I/O adapter in order to allow data to migrate between physical pages which receive accesses by the physical I/O adapter.
SOLUTION: When receiving a request for DMA to the physical page in a system memory from the I/O adapter, migration in progress display (MIP) bit in a transformation control entry (TCE) pointing to the physical page is examined. The MIP bit expresses whether or not migration to other locations in the system memory with respect to the physical page referred to in the TCE is in process. When the MIP bit expresses that the migration of the physical page is in progress, DMA from the I/O adapter is temporarily stopped, whereas other DMA operation to other physical pages in the system memory from other I/O adapters are permitted to continue.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种临时停止在物理I / O适配器中选择的DMA操作的机制，以便允许数据在物理I / O适配器接收的物理页之间迁移。 解决方案：当从I / O适配器接收到系统内存中的物理页面的DMA请求时，将检查指向物理页面的转换控制条目（TCE）中的迁移进度显示（MIP）位。 MIP位表示是否正在处理相对于TCE中引用的物理页面迁移到系统存储器中的其他位置。 当MIP位表示物理页面的迁移正在进行时，来自I / O适配器的DMA暂时停止，而允许来自其他I / O适配器的系统内存中的其他物理页面的其他DMA操作可以继续。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007272885A

公开(公告)日：2007-10-18

申请号：JP2007071774

申请日：2007-03-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARNDT RICHARD LOUIS ,  THURBER STEVE MARK

IPC: G06F12/10 ,  G06F13/28

CPC classification number: G06F11/141 ,  G06F12/08 ,  G06F12/1081

Abstract: PROBLEM TO BE SOLVED: To provide a method for managing DMA-write page fault by a computer using a pool of substitute write buffer pages.
SOLUTION: A platform of a computer system solves the DMA-write page fault for a page exclusive to an I/O adapter. The I/O adapter attempts to write DMA data in the page, it is determined that the page is not usable for writing, and the DMA data are written into data locations in the substitute page selected from the pool of substitute pages. Then, a flag is set to a flag location corresponding to each of the data locations. The flag locations correspond to the data locations, and when the flags are set, the flags represent that the DMA data reside in the data locations corresponding to the flag locations of the flags.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过计算机使用替代写入缓冲器页面池管理DMA写入页面错误的方法。 解决方案：计算机系统的平台解决了I / O适配器专用页面的DMA写入页面错误。 I / O适配器尝试在页面中写入DMA数据，确定该页面不能用于写入，并且将DMA数据写入从替代页面池中选择的替代页面中的数据位置。 然后，将标志设置为对应于每个数据位置的标志位置。 标志位置对应于数据位置，并且当标志被设置时，标志表示DMA数据驻留在对应于标志的标志位置的数据位置中。 版权所有（C）2008，JPO＆INPIT