公开(公告)号：DE2801271A1

公开(公告)日：1978-08-03

申请号：DE2801271

申请日：1978-01-13

Applicant: IBM

Inventor： RUPPRECHT HANS STEPHEN ,  SCHWENKER ROBERT OTTO

IPC: H01L29/73 ,  G01Q70/00 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/78

Abstract: A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.

公开(公告)号：DE1274232B

公开(公告)日：1968-08-01

申请号：DEJ0034082

申请日：1967-07-07

Applicant: IBM

Inventor： RUPPRECHT HANS STEPHEN ,  WOODALL JERRY MAC PHERSON

IPC: H01L21/00 ,  H01L33/00 ,  H01S5/30 ,  H01S5/32 ,  H05B33/16

公开(公告)号：DE3070293D1

公开(公告)日：1985-04-18

申请号：DE3070293

申请日：1980-12-04

Applicant: IBM

Inventor： MAGDO INGRID EMESE ,  RUPPRECHT HANS STEPHEN

IPC: H01L21/225 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/08 ,  H01L29/73 ,  H01L29/36 ,  H01L21/265 ,  H01L27/08

Abstract: Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.