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    1.
    发明专利
    未知

    公开(公告)号：DE2608214A1

    公开(公告)日：1976-10-07

    申请号：DE2608214

    申请日：1976-02-28

    Applicant: IBM

    Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN

    IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L29/73 ,  H01L29/8605 ,  H01C7/00

    Abstract: A semiconductor resistor structure for providing a high value resistance particularly adapted for space charge limited transistor applications, the resistor being fabricated in a semiconductor body having a resistivity in excess of 1 ohm cm., more preferably in semiconductor material that is nearly intrinsic. The resistor has two parallel elongated surface diffused regions in the body of an impurity similar to the background impurity of the body and having a surface concentration sufficient to provide an ohmic contact, the boundaries of said surface diffused regions defined by the interface where the impurity concentration of the diffused region is ten percent more than the impurity concentration of the background impurity of the body. In a preferred embodiment, the surface diffused regions are spaced such that the boundaries intersect with each other, and ohmic contact terminals to each of the diffused regions.

    METHOD FOR FORMING INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS
    2.
    发明专利
    METHOD FOR FORMING INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS 未知

    公开(公告)号：DE3177099D1

    公开(公告)日：1989-10-05

    申请号：DE3177099

    申请日：1981-06-23

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  MAGDO INGRID EMESE ,  MALAVIYA SHASHI DHAR

    IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/00 ,  H01L21/31

    Abstract: A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal or dielectric structure is substantially planar. The method of forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surfaces of the silicon body. A conductive layer is blanket desposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.

    4.
    发明专利
    未知

    公开(公告)号：DE2626193A1

    公开(公告)日：1976-12-30

    申请号：DE2626193

    申请日：1976-06-11

    Applicant: IBM

    Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN

    IPC: H01L29/78 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/73 ,  H01L21/72

    Abstract: A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BVceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.

    5.
    发明专利
    未知

    公开(公告)号：DE2612667A1

    公开(公告)日：1976-10-28

    申请号：DE2612667

    申请日：1976-03-25

    Applicant: IBM

    Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN ,  NESTORK WILLIAM JOHN

    IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535

    Abstract: A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide.

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