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    Read head with read track width defining layer that planarizes the write gap layer of a write head
    3.
    发明专利
    Read head with read track width defining layer that planarizes the write gap layer of a write head 未知

    公开(公告)号：AU1284700A

    公开(公告)日：2000-07-03

    申请号：AU1284700

    申请日：1999-11-24

    Applicant: IBM

    Inventor： SCHWENKER ROBERT OTTO ,  HWANG CHERNGYE

    IPC: G11B5/012 ,  G11B5/31 ,  G11B5/39

    Abstract: A read track width defining layer is employed for defining first and second side edges of a read sensor. The read track width defining layer preferably remains in the head to planarize the read head at first and second hard bias and lead layers so as to overcome a problem of write gap curvature in an accompanying write head. The read track width defining layer is defined by a subtractive process about a bilayer photoresist layer. The subtractive process is selective to the read track width defining layer over a read sensor material layer therebelow. Ion milling is then employed for defining first and second side edges of a read sensor layer employing the read track width defining layer as a mask. First and second hard bias and lead layers are then deposited which make contiguous junctions with the first and second side edges of each of the read sensor and read track width defining layers. The photoresist is then removed and the remainder of the read head is completed.

    PROCESS FOR PRODUCING BROAD AND DEEPLY PENETRATING ISOLATION TRENCHES IN A SEMICONDUCTOR SUBSTRATE
    4.
    发明专利
    PROCESS FOR PRODUCING BROAD AND DEEPLY PENETRATING ISOLATION TRENCHES IN A SEMICONDUCTOR SUBSTRATE 未知

    公开(公告)号：DE3071381D1

    公开(公告)日：1986-03-13

    申请号：DE3071381

    申请日：1980-06-03

    Applicant: IBM

    Inventor： HORNG CHENG TZONG ,  SCHWENKER ROBERT OTTO

    IPC: H01L21/76 ,  H01L21/033 ,  H01L21/263 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/90 ,  H01L23/52

    Abstract: 1. Method of making wide, deep recessed isolation trenches in a semiconductor substrate, where a) narrow, shallow trenches (16) are formed in the surface of the semiconductor substrate, said trenches having vertical sidewalls (18) and being separated from each other by profiles with a mesa cross section ; b) the bottom and sidewall surfaces (20, 18) of the trenches (16) formed in the semiconductor substrate, as well as the surfaces of the mesa profile are coated with a masking material (22) ; c) the masking material is removed from the bottom surfaces (20) of the trenches (16) and from the covering surfaces of the profiles by means of reactive ion etching ; d) the semiconductor substrate is exposed to a reactive ion etching, the masking material (24) remaining at the sidewalls of the trenches being used as an etching mask in order to produce a series of deep trenches separated from each other by means of narrow mesa sidewalls (28) ; e) the width of the sidewalls (28) is determined by the layer thickness of the masking material (22) ; and f) the material of the sidewalls is completely thermally oxidized.

    6.
    发明专利
    未知

    公开(公告)号：DE2801271A1

    公开(公告)日：1978-08-03

    申请号：DE2801271

    申请日：1978-01-13

    Applicant: IBM

    Inventor： RUPPRECHT HANS STEPHEN ,  SCHWENKER ROBERT OTTO

    IPC: H01L29/73 ,  G01Q70/00 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/331 ,  H01L21/78

    Abstract: A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.

    Read head with read track width defining layer that planarizes the write gap layer of a write head
    7.
    发明专利
    Read head with read track width defining layer that planarizes the write gap layer of a write head 未知

    公开(公告)号：GB2361801B

    公开(公告)日：2002-12-18

    申请号：GB0115773

    申请日：1999-11-24

    Applicant: IBM

    Inventor： CHANG HENRY CHINLIN ,  SCHWENKER ROBERT OTTO ,  HWANG CHERNGYE

    IPC: G11B5/012 ,  G11B5/31 ,  G11B5/39

    Abstract: A read track width defining layer is employed for defining first and second side edges of a read sensor. The read track width defining layer preferably remains in the head to planarize the read head at first and second hard bias and lead layers so as to overcome a problem of write gap curvature in an accompanying write head. The read track width defining layer is defined by a subtractive process about a bilayer photoresist layer. The subtractive process is selective to the read track width defining layer over a read sensor material layer therebelow. Ion milling is then employed for defining first and second side edges of a read sensor layer employing the read track width defining layer as a mask. First and second hard bias and lead layers are then deposited which make contiguous junctions with the first and second side edges of each of the read sensor and read track width defining layers. The photoresist is then removed and the remainder of the read head is completed.

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