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    Two dimensional addressing of matrix-vector register array
    2.
    发明专利
    Two dimensional addressing of matrix-vector register array 有权
    矩阵矢量寄存器阵列的二维寻址

    公开(公告)号：JP2005149492A

    公开(公告)日：2005-06-09

    申请号：JP2004314811

    申请日：2004-10-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： SANDON PETER A ,  WEST R MICHAEL P

    IPC: G06F7/00 ,  G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F9/34 ,  G06F15/00 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16

    CPC classification number: G06F9/3012 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30145 ,  G06F15/8084

    Abstract: PROBLEM TO BE SOLVED: To provide a processor and a method for processing matrix data. SOLUTION: The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N>2, M>2, K>1 and B>1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays so that the operation is performed with selectivity with respect to the data elements of the first array. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于处理矩阵数据的处理器和方法。 解决方案：处理器包括M个独立的向量寄存器文件，其适于集中存储L个数据元素的矩阵。 每个数据元素都有B位二进制位。 矩阵具有N行和M列，L = N * M。 每列有K个子列。 N> 2，M> 2，K> 1和B> 1。 每行和每个子列都是可寻址的。 处理器不会重复存储L个数据元素。 矩阵包括一组阵列，使得每个数组是矩阵的行或子列。 处理器可以执行对该组阵列的第一阵列执行操作的指令，使得相对于第一阵列的数据元素的选择性执行操作。 版权所有（C）2005，JPO＆NCIPI

    Machine code builder derived power consumption reduction
    3.
    发明专利
    Machine code builder derived power consumption reduction 有权
    机器代码制造商降低功耗

    公开(公告)号：JP2008165815A

    公开(公告)日：2008-07-17

    申请号：JP2008010936

    申请日：2008-01-21

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： COOK THOMAS E ,  GOVETT IAN R ,  KIM SUHWAN ,  KOSONOCKY STEPHEN V ,  SANDON PETER A

    IPC: G06F1/32 ,  G06F9/45 ,  G06F9/455 ,  G06F9/48

    CPC classification number: G06F8/4432 ,  Y02D10/41

    Abstract: PROBLEM TO BE SOLVED: To provide an architecture that does not suffer problems in a conventional technology. SOLUTION: A method for meeting requirements for performance of a microprocessor having a plurality of resources, which is executed in a computer having a processor and a memory, includes steps of reading pre-executable code into the memory, and building machine code from the pre-executable code. The pre-executable code includes an indicator indicating the start and end of a block of particular pre-executable code, and a constrained time required for completing execution of the block of particular pre-executable code. The step of building includes an instruction for computing a percentage difference between the constrained time and an actual execution time, and a step of inserting a system call in the machine code to pass the obtained difference to the operating system. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供在传统技术中不会遇到问题的架构。 解决方案：一种满足在具有处理器和存储器的计算机中执行的具有多个资源的微处理器性能要求的方法，包括以下步骤：将预执行代码读入存储器，以及构建机器代码 从预执行代码。 预执行代码包括指示特定预执行代码的块的开始和结束的指示符以及完成特定预执行代码块的执行所需的约束时间。 构建步骤包括计算约束时间和实际执行时间之间的百分比差的指令，以及在机器代码中插入系统调用以将获得的差异传递给操作系统的步骤。 版权所有（C）2008，JPO＆INPIT

    A METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT
    5.
    发明申请
    A METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT 审中-公开
    一种用于控制集成电路中的功耗的方法和装置

    公开(公告)号：WO2006034322A3

    公开(公告)日：2006-12-21

    申请号：PCT/US2005033766

    申请日：2005-09-21

    Applicant: IBM ,  KIM SUHWAN ,  KOSONOCKY STEPHEN V ,  SANDON PETER A

    Inventor： KIM SUHWAN ,  KOSONOCKY STEPHEN V ,  SANDON PETER A

    IPC: G06F1/26

    CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152

    Abstract: In a microprocessor based system (400), a programmable power management unit (PPMU) (414) dynamically controls the supply of power to a microprocessor (402) by analyzing the processing requirements of each instruction sequence or processing thread to determine whether a task should be performed by the PPMU (414) or passed to the microprocessor (402) according to a power management specification or power saving scheme. The PPMU (414) establishes the voltage level provided to the microprocessor via a power regulator/controller (412). External interrupts communicated to the system are handled by a universal interrupt controller (UIC) (410). The PPMU (414) may process an interrupt itself or forward execution to the microprocessor (402), activating the microprocessor from an idle state, if necessary. The PPMU (414) may also control power management functions internal to the processor, such as a clock generator divisor values or voltage island switching to dynamically scale performance in accordance with current processing requirements.

    Abstract translation: 在基于微处理器的系统（400）中，可编程电源管理单元（PPMU）（414）通过分析每个指令序列或处理线程的处理要求来动态地控制对微处理器（402）的供电，以确定是否应该 由PPMU（414）执行或根据功率管理规范或省电方案传递给微处理器（402）。 PPMU（414）通过功率调节器/控制器（412）建立提供给微处理器的电压电平。 传送到系统的外部中断由通用中断控制器（UIC）（410）处理。 如果需要，PPMU（414）可以自己处理中断或将执行转发到微处理器（402），从空闲状态激活微处理器。 PPMU（414）还可以控制处理器内部的功率管理功能，例如时钟发生器除数值或电压岛切换，以根据当前处理要求动态地缩放性能。

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