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    System, device, and method of providing counter for scaling operating frequency of microprocessor
    2.
    发明专利
    System, device, and method of providing counter for scaling operating frequency of microprocessor 有权
    提供微处理器操作频率的计数器的系统，设备和方法

    公开(公告)号：JP2007200303A

    公开(公告)日：2007-08-09

    申请号：JP2006351591

    申请日：2006-12-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DR CEDRIC LICHTENAU ,  MARTIN RECKTENWALD ,  SCHMIDT ANDREAS ,  PFLUEGER THOMAS ,  KUENZER JENS ,  ROLF HILGENDORF B

    IPC: G06F1/04 ,  G06F1/08

    CPC classification number: G06F1/14 ,  G04F10/04 ,  H03L7/06

    Abstract: PROBLEM TO BE SOLVED: To provide a system, a device, and a method of providing an accurate time-based counter for scaling an operating frequency of a microprocessor. SOLUTION: This system, this device, and this method make use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of a clock generation circuit of the microprocessor and is used to be fed to external and internal timebase logic and a timebase accumulator counter. The timebase accumulator counter accumulates tick events from the timebase logic between two core clocks. The accumulated value is transferred to a core clock domain on every clock edge of a scalable clock, and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种系统，设备和提供用于缩放微处理器的工作频率的精确的基于时间的计数器的方法。 解决方案：该系统，该装置和该方法利用基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL并且被用于馈送到 外部和内部时基逻辑和时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器被复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。 版权所有（C）2007，JPO＆INPIT

    METHOD AND SYSTEM FOR ISSUING INSTRUCTION
    3.
    发明专利
    METHOD AND SYSTEM FOR ISSUING INSTRUCTION 失效

    公开(公告)号：JPH10283178A

    公开(公告)日：1998-10-23

    申请号：JP4930398

    申请日：1998-03-02

    Applicant: IBM

    Inventor： GETZLAFF KLAUS JOERG ,  LEPPLA BERND ,  PFEFFER ERWIN ,  PFLUEGER THOMAS ,  WITHELM BIRGIT

    IPC: G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To issue an instruction to an execution unit even at the time of a continuous sequence and back-to-back in a random processing system by setting the valid bit of the target operand before the target operand of the instruction becomes usable. SOLUTION: The instruction is taken out from an instruction memory 100 and successively buffered in an instruction cache 101, then the instruction is decoded to a common internal instruction format and then, the instruction is transferred to a reservation station 103. In the reservation station 103, the instruction stands by until issuance to one of function units can be performed. In such a random processing system, the valid bit of the target operand is set before the target operand of the instruction becomes usable. A source operand is generated as the target operand of a preceding instruction and the instruction is immediately issued when the valid bit is set to the entire source operands.

    USING 3D INTEGRATED DIFFRACTIVE GRATINGS IN SOLAR CELLS
    5.
    发明申请
    USING 3D INTEGRATED DIFFRACTIVE GRATINGS IN SOLAR CELLS 审中-公开
    在太阳能电池中使用3D集成衍射光栅

    公开(公告)号：WO2009090123A3

    公开(公告)日：2010-01-14

    申请号：PCT/EP2009050094

    申请日：2009-01-07

    Applicant: IBM ,  FERTIG MATTHIAS ,  PFLUEGER THOMAS ,  MORF THOMAS E ,  MOLL NIKOLAJ

    Inventor： FERTIG MATTHIAS ,  PFLUEGER THOMAS ,  MORF THOMAS E ,  MOLL NIKOLAJ

    IPC: H01L25/04 ,  H01L27/146 ,  H01L31/04

    CPC classification number: H01L31/0687 ,  H01L25/043 ,  H01L31/02167 ,  H01L31/043 ,  H01L2924/0002 ,  Y02E10/544 ,  Y02P70/521 ,  H01L2924/00

    Abstract: A multi- junction opto-electronic device comprising a stack of wavelength selective absorption layers is proposed. The absorption layers comprise each a first layer with a grating of a specific pitch defining the wavelength of the incident light to be absorbed within a subjacent second electrically active layer itself on a third electrically inactive layer. The second electrically active layer within the different absorption layers is in electrical connection with lateral contacts to extract the electrical charge carriers generated by the absorbed incident light within the active layer. The grating within the first layer of the absorption layers is defined by periodic stripes of specific width depending on the wavelength to be absorbed by the respective absorption layers. The period of the stripes alignment is defined by the pitch of the grating. Advantageously, ordinary silicon technology can be used.

    Abstract translation: 提出了包括一叠波长选择吸收层的多结光电子器件。 吸收层包括每个具有特定间距的光栅的第一层，其限定入射光的波长，以在第三电无活性层上的相邻的第二电活性层本身内被吸收。 不同吸收层内的第二电活性层与横向触点电连接以提取由活性层内的吸收的入射光产生的电荷载流子。 吸收层的第一层内的光栅由具有特定宽度的周期性条纹限定，这取决于要被各个吸收层吸收的波长。 条纹对准的周期由光栅的间距限定。 有利地，可以使用普通的硅技术。

    Memory matrix which allows multiple simultaneous writing access with write-through
    7.
    发明专利
    Memory matrix which allows multiple simultaneous writing access with write-through 未知

    公开(公告)号：DE19821581A1

    公开(公告)日：1999-01-07

    申请号：DE19821581

    申请日：1998-05-14

    Applicant: IBM

    Inventor： LOEFFLER PETER ,  PFEFFER ERWIN ,  PFLUEGER THOMAS ,  TAST HANS-WERNER

    IPC: G11C8/16 ,  G11C7/00 ,  G11C5/02

    Abstract: The matrix uses a quantity of memory cells, along with a process for storing data in one quantity and a process for calling data from another quantity. The quantity of memory allows the functionality of a cell with repeated write connections by means of a quantity of cells with simple write connection and allows multiple simultaneous write accesses. The information, which is contained in the quantity of memory, is presented through all the memories together. It can be retrieved by a read function, which records on a subset of the named quantity. Stored data have three subsets A,B and C, operated on by read and write functions. Writing access is accomplished in three steps. First the contents of all memory, which are not modified, are read. As next values are calculated in a way, which are to be entered in a subset B of the named quantity of memory. The contents and the values of the subset B together represent the desired result. Device for reading contents of subset C of data uses data stored jointly.

    8.
    发明专利
    未知

    公开(公告)号：DE69122860T2

    公开(公告)日：1997-04-03

    申请号：DE69122860

    申请日：1991-07-06

    Applicant: IBM

    Inventor： TAST HANS-WERNER ,  PFLUEGER THOMAS ,  GETZLAFF KLAUS JOERG DIPL ING

    IPC: G06F7/00 ,  G06F7/76 ,  H03K17/00 ,  H03M7/00 ,  H04J3/04

    Abstract: A multiplexer circuit is described which is built up from a series of smaller submultiplexers (241-247, 251-254). It selects a number of adjacent bits, bytes or words from one register and places them in the same order in a second register. The multiplexer can be used in cache memories or instruction buffers.

    9.
    发明专利
    未知

    公开(公告)号：DE69122860D1

    公开(公告)日：1996-11-28

    申请号：DE69122860

    申请日：1991-07-06

    Applicant: IBM

    Inventor： TAST HANS-WERNER ,  PFLUEGER THOMAS ,  GETZLAFF KLAUS JOERG DIPL ING

    IPC: G06F7/00 ,  G06F7/76 ,  H03K17/00 ,  H03M7/00 ,  H04J3/04

    Abstract: A multiplexer circuit is described which is built up from a series of smaller submultiplexers (241-247, 251-254). It selects a number of adjacent bits, bytes or words from one register and places them in the same order in a second register. The multiplexer can be used in cache memories or instruction buffers.

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