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    DEVICE AND METHOD FOR MUTUAL DYNAMIC CONVERSION BETWEEN DIFFERENT INSTRUCTION CODES
    2.
    发明专利
    DEVICE AND METHOD FOR MUTUAL DYNAMIC CONVERSION BETWEEN DIFFERENT INSTRUCTION CODES 失效

    公开(公告)号：JPH10240524A

    公开(公告)日：1998-09-11

    申请号：JP2892698

    申请日：1998-02-10

    Applicant: IBM

    Inventor： HILGENDORF ROLF ,  SCHWERMER HARTMUT ,  SOELL WERNER

    IPC: G06F9/318

    Abstract: PROBLEM TO BE SOLVED: To obtain the possibility of parallel decoding of instructions and to make easy alterations of a conversion path by using reconstitution information corresponding to the instruction of the code and reconstituting instruction elements of the instruction of the code according to the reconstitution information. SOLUTION: The reconstitution information needed to convert an external instruction 100 into one group of internal instructions 101 is included in a conversion table 106. Respective entries 105 of the table 106 correspond to one instruction 100 of an external code to determine how instruction elements of this specific instruction should be reconstituted to form corresponding internal instructions 101. Then the elements of the external instruction like immediate data 110, logical register identifiers 111 and 112, status information, and others 113 and 114 are reconstituted by one group of multiplexers 120 to 124. The outputs of the respective multiplexers are written directly in corresponding fields.

    DEVICE FOR EXECUTING SUB-ROUTINE CALLING AND RETURN OPERATION AND METHOD THEREFOR
    3.
    发明专利
    DEVICE FOR EXECUTING SUB-ROUTINE CALLING AND RETURN OPERATION AND METHOD THEREFOR 失效

    公开(公告)号：JPH11259298A

    公开(公告)日：1999-09-24

    申请号：JP925899

    申请日：1999-01-18

    Applicant: IBM

    Inventor： HILGENDORF ROLF ,  LAUB OLIVER ,  TAST HANS-WERNER

    IPC: G06F9/38 ,  G06F9/42 ,  G06F12/0875

    Abstract: PROBLEM TO BE SOLVED: To reduce a processing time for defining the target address of a sub-routine return instruction. SOLUTION: In a computer having a processor equipped with an instruction prefetch mechanism including a branch history table for storing the target address of plural branch instructions to be found in an instruction stream, a sub-routine calling and return operation is executed. In this case, the branch history table 22 includes a latent calling instruction tag and a return instruction tag. Each time the latent sub-routine calling instruction is found in the prefetch instruction stream, a pair of addresses including the calling target address of the instruction and the next successive instruction address are stored in a return identification stack 24. Then, a detected branch instruction activates associative retrieval for the next successive instructing part identifying the branch instruction as the return instruction by a matched entry in the return identification stack. Then, a pair of addresses included in the matched entry are transferred to a return cache 30 provided in parallel to the branch history table.

    8.
    发明专利
    未知

    公开(公告)号：DE10121792C2

    公开(公告)日：2003-09-25

    申请号：DE10121792

    申请日：2001-05-04

    Applicant: IBM

    Inventor： BAROWSKY HARALD STEFAN ,  HILGENDORF ROLF

    IPC: G06F9/345 ,  G06F9/38

    Abstract: This invention is a method and system for hybrid prediction of load addresses and/or values. The new scheme for value prediction provides prediction based on last values and strides, as well as context prediction, without the use of a sophisticated switching scheme between several predictors. The system collects patterns of deltas of subsequent values instead of the values itself in a first table. Thus, a last value prediction can be achieved by predicting a 'pattern' of just one stride equal to zero. A stride predictor uses a pattern of one constant stride. And a certain pattern of values is modeled by recording the pattern of deltas between the values and adding the deltas to the last value. The switching scheme is inherently included in the system itself and operates basically by immediate evaluation of counters in the pattern history table.

    Branch-addresses prediction method e.g. for microprocessors, requires directly polling an instruction for hits found in appropriate address source device
    9.
    发明专利
    Branch-addresses prediction method e.g. for microprocessors, requires directly polling an instruction for hits found in appropriate address source device 未知

    公开(公告)号：DE10232488A1

    公开(公告)日：2003-02-27

    申请号：DE10232488

    申请日：2002-07-18

    Applicant: IBM

    Inventor： HILGENDORF ROLF

    IPC: G06F9/38 ,  G06F9/32

    Abstract: A method of predicting branch-addresses for a given branch instruction involves operating an additional (second) address source device (conversion buffer) (32) for storing a number of actually used branch-addresses. An instruction is directly polled for hits found in the second address source device (32), and the address made ready by this source (32) is then compared (30) with the address resulting from the hit in this source (32). Direct polling of the relevant instruction is carried out when these addresses are identical, and the instruction polling is repeated using the instruction address outputted by the first address source (branch target buffer) (16) when the addresses are not identical An Independent claim is given for a computer processing unit

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