公开(公告)号：JPS62105444A

公开(公告)日：1987-05-15

申请号：JP19300186

申请日：1986-08-20

Applicant: IBM

Inventor： NOBLE JR WENDELL P ,  SCHEUERLEIN ROY E ,  WALKER WILLIAM W

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/265 ,  H01L21/762 ,  H01L27/10 ,  H01L27/105

公开(公告)号：MY118271A

公开(公告)日：2004-09-30

申请号：MYPI9902978

申请日：1999-07-14

Applicant: IBM

Inventor： SCHEUERLEIN ROY E

IPC: G11C11/14 ,  G11C11/15 ,  H01L27/115

Abstract: A NONVOLATILE MEMORY CELL (20, 40, 50, 60, 70) INCLUDES A SUBSTRATE (21, 100), A DIODE (22), A FIRST CONDUCTIVE LINE (12, 23), A MAGNETIC TUNNEL JUNCTION DEVICE (25), A BY-PASS CONDUCTOR (29) AND A SECOND CONDUCTIVE LINE (13, 27). THE DIODE IS FORMED IN THE SUBSTRATE AND INCLUDES AN N-TYPE REGION (22A) AND A P-TYPE REGION (22B). THE FIRST CONDUCTIVE LINE IS FORMED ON THE SUBSTRATE AND IS ELECTRICALLY CONNECTED TO THE N-TYPE REGION OF THE DIODE. THE MAGNETIC TUNNEL JUNCTION DEVICE IS FORMED ON THE FIRST CONDUCTIVE LINE. THE BY-PASSCONDUCTOR ELECTRICALLY CONNECTS THE P-TYPE REGION OF THE DIODE TO THE MAGNETIC TUNNEL JUNCTION DEVICE. THE SECOND CONDUCTIVE LINE IS FORMED ON AND IS ELECTRICALLY CONNECTED TO THE MAGNETIC TUNNEL JUNCTION DEVICE.

公开(公告)号：CA1163714A

公开(公告)日：1984-03-13

申请号：CA363544

申请日：1980-10-29

Applicant: IBM

Inventor： SCHEUERLEIN ROY E

IPC: G11C11/401 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C11/24 ,  G11C5/10 ,  G11C11/40

Abstract: One Device Field Effect Transistor (FET) AC Stable Random Access Memory (RAM) Array Disclosed is an integrated circuit electronic memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region in and out of the capacitive storage region. Each memory cell also has a bit line contact region which is shared with an adjacent memory cell. The word lines are arranged in rows in a substantially equidistant parallel relationship, each word line passing, in succession, over the storage region of a first one of the memory cells and electrically integral with the gate region of a second one of the memory cells. The column arrangement of memory cells is interdigitated such that the memory cells associated with a single bit line are arranged in first and second parallel lines along both the left and right sides of each bit line. Thus, the bit line is arranged in a zig-zag configuration alternately contacting memory cells arranged along its left and right side. FI9-79-006

公开(公告)号：MY123905A

公开(公告)日：2006-06-30

申请号：MYPI9904644

申请日：1999-10-27

Applicant: IBM

Inventor： KOCH ROGER HILSON ,  SCHEUERLEIN ROY E

IPC: G11C11/15 ,  H01L27/10 ,  G11C11/16

Abstract: A NONVOLATILE MAGNETIC MEMORY ARRAY USES MAGNETIC MEMORY CELLS THAT ARE FORMED IN TWO TYPES OF SHAPES. THE CELLS LIE AT THE INTERSECTIONS OF ROWS AND COLUMNS OF ELECTRICALLY CONDUCTIVE LINES, WHICH SERVE AS THE CONDUCTIVE PATHS FOR THE WRITE CURRENTS USED TO CHANGE THE MAGNETIZATION STATES OF THE MAGNETIC CELLS. THE TWO TYPES OF CELLS HAVE SHAPES THAT ARE MIRROR IMAGES OF EACH OTHER, I.E, THE SHAPE OF THE SECOND TYPE OF CELL IS ARRIVED AT BY ROTATING THE FIRST TYPE OF CELL 180 DEGREES ABOUT AN AXIS THROUGH THE CELL. THE TWO TYPES OF CELLS ARE THUS A PAIR OF ASYMMETRIC CELLS BECAUSE THEY ARE ASYMMETRIC IN REGARD TO THE PREDOMINANT AXIS OF MAGNETIZATION. IN THE PREFERRED PATTERN, EACH OF THE CELLS HAS A PARALLELOGRAM SHAPE WITH A LENGTH AND A WIDTH WITH THE PREDOMINANT AXIS OF MAGNETIZATION LYING SUBSTANTIALLY ALONG A LINE BETWEEN THE ACUTE CORNERS OF THE PARALLELOGRAM. THE TWO TYPES OF CELLS ARE PREFERABLY ARRANGED IN THE ARRAY IN AN ALTERNATING CHECKERBOARD PATTERN, WHICH MEANS THAT ONE TYPE OF CELL IS SURROUNDED BY NEIGHBORING CELLS OF THEOTHER TYPE. BECAUSE THE PREDOMINANT AXIS OF MAGNETIZATION OF ALL NEIGHBORING CELLS IS DIFFERENT FROM THE PREDOMINANT AXIS OF MAGNETIZATION OF THE CELL SELECTED FOR WRITING, THERE IS SUBSTANTIALLY LESS LIKELIHOOD THAT ADJACENT NEIGHBORING CELLS WILL ALSO BE WRITTEN TO. THE MEMORY ARRAY MAY BE FORMED USING EITHER MAGNETIC TUNNEL JUNCTION (MTJ) CELLS OR GIANT MAGNETORESISTANCE (GMR) CELLS.(FIG. 6)

公开(公告)号：CA1213981A

公开(公告)日：1986-11-12

申请号：CA452130

申请日：1984-04-16

Applicant: IBM

Inventor： SCHEUERLEIN ROY E

IPC: G11C11/405 ,  G11C11/401 ,  G11C11/4097 ,  G11C11/24

Abstract: Shared Access Lines Memory Cells A memory array is provided which includes a common sense line to which is connected a first storage capacitor through first switching means and a second storage capacitor through second switching means, with a common word line connected to the control electrodes of the first and second switching means, a first bit line connected to a plate of the first storage capacitor and a second bit line connected to a plate of the second storage capacitor. Data is stored into or read from the first storage capacitor by selecting the common word line and the first bit line and data is stored into and read from the second storage capacitor by selecting the common word line and the second bit line, with the data from both storage capacitors being detected on the common sense line.

公开(公告)号：DE69125542T2

公开(公告)日：1997-09-25

申请号：DE69125542

申请日：1991-07-26

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  SCHEUERLEIN ROY E

IPC: G11C11/409 ,  G11C11/4091

Abstract: A dynamic random access memory comprises a sense amplifier including a latch (10) comprising a pair of NMOS FETs (TN1,TN2) with their gates and drains cross coupled and with their sources connected to a common node. A pair of bitlines (BL,BLN) are coupled to the cross coupled nodes of the latch (10). An FET (TP5) enables the bitlines to be precharged to a precharge voltage. A latch driving circuit (16) is coupled to the common node of the latch (10). The latch driving circuit (16) comprises means (TN5,TN6) for coupling a reference voltage to the common node for activating the latch (10) after the bitlines have been precharged, and means (TN7,20) for controlling the voltage of the common node in such a manner that the downward voltage swing of the lower level bitline towards the reference voltage, produced by activation of the latch (10), is limited to a predetermined voltage level higher than the reference voltage. This advantageously provides a high speed memory operation and reduced power consumption.

公开(公告)号：DE69125542D1

公开(公告)日：1997-05-15

申请号：DE69125542

申请日：1991-07-26

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  SCHEUERLEIN ROY E

IPC: G11C11/409 ,  G11C11/4091

Abstract: A dynamic random access memory comprises a sense amplifier including a latch (10) comprising a pair of NMOS FETs (TN1,TN2) with their gates and drains cross coupled and with their sources connected to a common node. A pair of bitlines (BL,BLN) are coupled to the cross coupled nodes of the latch (10). An FET (TP5) enables the bitlines to be precharged to a precharge voltage. A latch driving circuit (16) is coupled to the common node of the latch (10). The latch driving circuit (16) comprises means (TN5,TN6) for coupling a reference voltage to the common node for activating the latch (10) after the bitlines have been precharged, and means (TN7,20) for controlling the voltage of the common node in such a manner that the downward voltage swing of the lower level bitline towards the reference voltage, produced by activation of the latch (10), is limited to a predetermined voltage level higher than the reference voltage. This advantageously provides a high speed memory operation and reduced power consumption.