公开(公告)号：EP2672633A4

公开(公告)日：2014-03-26

申请号：EP12754784

申请日：2012-03-02

Applicant: IBM

Inventor： NAKANO DAIJU ,  KATAYAMA YASUNAO ,  KOHDA YASUTERU

IPC: H04B7/005

CPC classification number: H04L27/01 ,  H04L7/0029 ,  H04L7/10 ,  H04L25/03038 ,  H04L27/22 ,  H04L27/38 ,  H04L2025/03471 ,  H04L2025/03605 ,  H04L2025/03687

公开(公告)号：EP1753031A4

公开(公告)日：2011-06-01

申请号：EP05743368

申请日：2005-05-26

Applicant: IBM

Inventor： KATAYAMA YASUNAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/772 ,  H01L29/88 ,  H03K19/02 ,  H03K19/20

CPC classification number: H01L29/772 ,  H01L29/88 ,  Y10S977/762 ,  Y10S977/774

公开(公告)号：JP2012123561A

公开(公告)日：2012-06-28

申请号：JP2010272947

申请日：2010-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TAKANO KOJI ,  KATAYAMA YASUNAO

IPC: G06F7/00

CPC classification number: G06F17/142 ,  G06F17/141

Abstract: PROBLEM TO BE SOLVED: To reduce the rounding error of a high speed Fourier transformation (FFT) arithmetic operation.SOLUTION: Data appearing as an irrational number (√, square root) among rotation factors on a complex plane included in a butterfly arithmetic operation (8p) are not intentionally calculated, but preserved in a memory installed in one stage among a plurality of stages of an FFT integrated into a pipe line in multi-stages, and when the data reappear in the subsequent stage, an arithmetic operation to multiply two rotation factors is performed. Thus, it is possible to eliminate any rounding error during the butterfly arithmetic operation (8p) of a radix 8(radix-8). Furthermore, it is possible to apply this invention to cover more stages by the butterfly arithmetic operation of a radix 2(radix-s) or a radix (radix-4).

Abstract translation: 要解决的问题：减少高速傅里叶变换（FFT）算术运算的舍入误差。

解决方案：在蝴蝶算术运算（8p）中包含的复平面上的旋转因子中出现的无理数（√，平方根）的数据不是有意计算的，而是保存在多个安装在一个阶段中的存储器中 在多级中集成到管线中的FFT的阶段，并且当数据在后续阶段再次出现时，执行乘以两个旋转因子的算术运算。 因此，可以在基数8（基数-8）的蝶形运算（8p）期间消除任何舍入误差。 此外，可以通过基数2（基数s）或基数（基数-4）的蝶形运算来应用本发明来覆盖更多的级。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011114613A

公开(公告)日：2011-06-09

申请号：JP2009269606

申请日：2009-11-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKANO DAIKI ,  KATAYAMA YASUNAO

IPC: H04L7/08

CPC classification number: H04L7/042 ,  H04W88/02

Abstract: PROBLEM TO BE SOLVED: To provide a radio receiver, a radio communication system, a radio communication method and a program for achieving synchronization in high speed radio communication. SOLUTION: The radio receiver 200 includes: a sampling part 210 which samples a baseband signal to be transmitted from a radio transmitter by fractional multiples of symbol rate to generate fractional multiple sample data; a providing part 220 in which the radio transmitter provides reference data in which a known symbol system to be arranged in a frame is interpolated by rate of fractional multiples, while reflecting an overall filter response of the radio transmitter and the radio receiver; a calculation part 230 which calculates evaluation data for evaluating a degree of matching of waveform between the fractional multiple sample data and the reference data; an estimation part 240 which estimates reference timing from a shift amount in which the degree of matching of the waveform of the evaluation data shows maximum; and a conversion part 250 which converts the fractional multiple sample data on the basis of the reference timing to restore data of the symbol rate. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种无线电接收机，无线电通信系统，无线电通信方法和用于实现高速无线电通信中的同步的程序。 解决方案：无线电接收机200包括：采样部分210，其通过符号速率的分数倍采样从无线电发射机发射的基带信号，以产生分数多个采样数据; 提供部分220，其中无线电发射机提供参考数据，其中通过分数倍的速率来插值要布置在帧中的已知符号系统，同时反映无线电发射机和无线电接收机的整体滤波器响应; 计算部230，计算用于评价分数多样本数据和参考数据之间的波形的匹配度的评价数据; 从评估数据的波形的匹配程度显示最大的偏移量估计基准定时的估计部240; 以及转换部分250，其基于参考定时转换分数多个样本数据，以恢复符号率的数据。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009278678A

公开(公告)日：2009-11-26

申请号：JP2009196510

申请日：2009-08-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KATAYAMA YASUNAO ,  NAKANO DAIKI

IPC: H03M13/29 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To improve a recovery rate of packets while efficiently utilizing an optimum quantity of redundant information.
SOLUTION: This invention discloses a Partially-Overlapped Block (POB) code as a new encoding system that is structured such that a plurality of block codes different from one another are combined in a form where they partially overlap one another. A decoding method is also disclosed corresponding to the encoding system. Further, a method for recovering a plurality of packets using a loss correction capability of this code is disclosed. The larger number of packets than the number of added redundant packets per frame can be recovered by well reusing redundant information of neighboring frames without increasing the asymptotic calculation quantity of a decoding algorithm.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提高数据包的恢复速率，同时有效利用最佳数量的冗余信息。 解决方案：本发明公开了一种作为新编码系统的部分重叠块（POB）代码，其被构造为使得彼此不同的多个块代码以彼此部分重叠的形式组合。 对应于编码系统也公开了解码方法。 此外，公开了一种使用该代码的损失校正能力来恢复多个分组的方法。 通过在不增加解码算法的渐近计算量的情况下，重新使用相邻帧的冗余信息，可以恢复比每帧增加的冗余分组数更多的分组数。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2002023999A

公开(公告)日：2002-01-25

申请号：JP2000185582

申请日：2000-06-21

Applicant: IBM

Inventor： MORIOKA SUMIO ,  KATAYAMA YASUNAO

IPC: G06F7/552 ,  G06F7/72 ,  G09C1/00 ,  H03M13/00 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To provide a multiplication module for multiplying m-bit data on a Galois field GF (2m) (m>=1). SOLUTION: This multiplication module is provided with 1st and 2nd power exponent computing means u1 and u2 to which 1st m-bit data is inputted from a 1st input part, a 1st multiplying means u3 to which the 1st m-bit data and an output from the 1st power exponent computing mean are inputted, a 2nd multiplying means u4 to which 2nd m-bit data from a 2nd input part and an output from the means u2 are inputted and a selecting means u5 to which an output signal of a the 2nd multiplying means and the 2nd m-bit data are inputted. A 1st control signal S1 is inputted to the 1st power exponent computing means, a 2nd control signal S2 is inputted to the 2nd power exponent computing means, a 3rd control signal S0 for controlling the output of the selecting means is inputted to the selecting means, the 1st multiplying means outputs a 1st output signal, and the selecting means outputs a 2nd output signal.

公开(公告)号：JP2000114984A

公开(公告)日：2000-04-21

申请号：JP26849398

申请日：1998-09-22

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  MORIOKA SUMIO

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To provide a decoding circuit for a Reed-Solomon code which is fast and low power consumption. SOLUTION: A syndrome calculating circuit 1 calculates a syndrome Sj (j=0, 1,..., 2t-1) from a 1st codeword Yi (i=0, 1,..., n-1) that may include an error. A coefficient calculating circuit 3 calculates the coefficient Λk of an error position polynomial corresponding to the number of estimated errors (e) (e

公开(公告)号：JP2011066629A

公开(公告)日：2011-03-31

申请号：JP2009214679

申请日：2009-09-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OBA NOBUYUKI ,  KODA YASUTERU ,  KATAYAMA YASUNAO

IPC: H04L27/36 ,  H04L27/18 ,  H04L27/22 ,  H04L27/38

CPC classification number: H03M1/0624 ,  H03M1/0836 ,  H03M1/66

Abstract: PROBLEM TO BE SOLVED: To detect and correct a phase shift between an I data clock and a Q data clock in a DAC or an ADC used for a modulator or a demodulator regarding a quadrature modulator in a high-speed radio communication. SOLUTION: A phase comparison is made by receiving an I data clock 621 and a Q data clock 631 outputted from an I-DAC and a Q-DAC. A phase comparator having a function of outputting a data clock DELAY signal to a Q-DAC 630 is provided. For phase adjustment, the I data clock and the Q data clock are compared by an XOR, the result is sampled by another phase clock asynchronous with the data clock, and the frequency of a sampling value=0 and the frequency of a sampling value=1 are respectively counted to determine a phase shift of the data clocks from the counts. A delay device 680 to be placed within the DAC or an FPGA is further provided, and a 90-degree shift and a 270-degree shift are discriminated by using a delay function of the data clock. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：检测和校正在用于高速无线电通信中的关于正交调制器的调制器或解调器的DAC或ADC中的I数据时钟和Q数据时钟之间的相移。 解决方案：通过接收从I-DAC和Q-DAC输出的I数据时钟621和Q数据时钟631进行相位比较。 提供了具有向Q-DAC 630输出数据时钟DELAY信号的功能的相位比较器。 对于相位调整，I数据时钟和Q数据时钟通过XOR进行比较，结果由与数据时钟异步的另一个相位时钟进行采样，采样值的频率= 0，采样值的频率= 分别计数1以从计数确定数据时钟的相移。 进一步提供放置在DAC或FPGA内的延迟装置680，并通过使用数据时钟的延迟功能来鉴别90度移位和270度移位。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2002335166A

公开(公告)日：2002-11-22

申请号：JP2001196145

申请日：2001-06-28

Applicant: IBM

Inventor： YAMANE TOSHIYUKI ,  KATAYAMA YASUNAO ,  MORIOKA SUMIO

IPC: G06F11/10 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To provide a signal processing method, a signal processing system, a program for the signal processing, and a computer-connectable recording medium for recording the processing program. SOLUTION: The signal processing method for the digital signal includes a step of formulating a Yule-Walker equations in a prescribed form of a matrix of elements in a Galois field (2 ) and a vector, including the element as a factor in the Galois field (2 ), a step of returning the solution of the equation to a calculation of a symmetric matrix in a Jacobi's formula, a step of determining the number of errors as the size of the maximum matrix corresponding to the solution other than zero, and a step of determining whether or not the number of errors is equal to the maximum number of correctable errors.

公开(公告)号：JPH10293782A

公开(公告)日：1998-11-04

申请号：JP4918098

申请日：1998-03-02

Applicant: IBM

Inventor： WIN K RUK ,  WEI FAN ,  KATAYAMA YASUNAO

IPC: H01L27/04 ,  G06F17/50 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To perform compilation to integrated logic and a DRAM system on a single chip from the hardware description language and wiring description of design composed of a DRAM macro and a logic macro by integrating logic and a DRAM memory to the same chip. SOLUTION: From a single processor memory chip for which a processor 21 is connected to a DRAM 22 by on-chip mutual connection 23, off-chip mutual connection disappears. Thus, by DRAM I/O and internal control, a memory data transfer rate utilizable for the processor 21 is raised for many digits. By integrating the processor 21 and the DRAM 22 to the same chip, the length of the on-chip mutual connection 23 and a capacitive load are substantially reduced and optimization is performed further by making the length of a wire shortest. As a result, a system clock speed is accelerated further and performance is improved.