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公开(公告)号：SG45138A1
公开(公告)日：1998-01-16
申请号：SG1996000352
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELLIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：DE69424229D1
公开(公告)日：2000-06-08
申请号：DE69424229
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：BR9402666A
公开(公告)日：1995-05-02
申请号：BR9402666
申请日：1994-07-08
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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Patent Agency Ranking
公开(公告)号：ES2145100T3
公开(公告)日：2000-07-01
申请号：ES94304678
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：AT192614T
公开(公告)日：2000-05-15
申请号：AT94304678
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：DE69424229T2
公开(公告)日：2000-11-30
申请号：DE69424229
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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7.发明专利
公开(公告)号：CA2122170A1
公开(公告)日：1995-01-09
申请号：CA2122170
申请日：1994-04-26
Applicant: IBM
Inventor： HASSNER MARTIN A , KARNIN EHUD D , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: COMBINATION PARALLEL/SERIAL EXECUTION OF SEQUENTIAL ALGORITHM FOR DATA COMPRESSION/DECOMPRESSION An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer compresses an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：CA2057666A1
公开(公告)日：1992-07-23
申请号：CA2057666
申请日：1991-12-13
Applicant: IBM
Inventor： HASSNER MARTIN , SCHWIEGELSHOHN UWE , WINOGRAD SHMUEL
Abstract: SA9-91-003 Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. A computational loop has one branching condition that branches into two straight-line loops. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two loops being required to decode t symbols in error. These loops are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in said other loop being paired with a multiplication operation in the next iteration of said one loop. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed.
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