Data storage array
    1.
    发明申请
    Data storage array 审中-公开
    数据存储阵列

    公开(公告)号:WO2005006173A3

    公开(公告)日:2006-06-08

    申请号:PCT/EP2004051385

    申请日:2004-07-07

    Abstract: A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.

    Abstract translation: 包含三个数据存储单元,三个检查存储单元和耦合到三个数据的阵列控制器和三个检查存储单元的数据存储子系统可以容忍任何三个数据的故障,并且检查存储单元可能在存储在 数据存储子系统丢失。 信息作为对称的最大距离分离码存储在数据存储子系统上,例如Winograd代码,Reed Solomon码,EVENODD码或EVENODD码的导数。 阵列控制器确定检查存储单元的内容,使得数据存储单元和检查存储单元的任何三个擦除可以由阵列控制器校正。 阵列控制器仅使用六个IO操作来更新包含在任何一个数据存储单元和检查存储单元中的数据块。

    DATA STORAGE ARRAY
    2.
    发明申请
    DATA STORAGE ARRAY 审中-公开
    数据存储阵列

    公开(公告)号:WO2005006173A9

    公开(公告)日:2006-02-23

    申请号:PCT/EP2004051385

    申请日:2004-07-07

    Abstract: A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.

    Abstract translation: 包含三个数据存储单元,三个检查存储单元和耦合到三个数据的阵列控制器和三个检查存储单元的数据存储子系统可以容忍任何三个数据的故障,并且检查存储单元可能在存储在 数据存储子系统丢失。 信息作为对称的最大距离分离码存储在数据存储子系统上,例如Winograd代码,Reed Solomon码,EVENODD码或EVENODD码的导数。 阵列控制器确定检查存储单元的内容,使得数据存储单元和检查存储单元的任何三个擦除可以由阵列控制器校正。 阵列控制器仅使用六个IO操作来更新包含在任何一个数据存储单元和检查存储单元中的数据块。

    MODULAR IMPLEMENTATION FOR A PARALLELIZED KEY EQUATION SOLVER FOR LINEAR ALGEBRAIC CODES

    公开(公告)号:CA2057666A1

    公开(公告)日:1992-07-23

    申请号:CA2057666

    申请日:1991-12-13

    Applicant: IBM

    Abstract: SA9-91-003 Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. A computational loop has one branching condition that branches into two straight-line loops. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two loops being required to decode t symbols in error. These loops are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in said other loop being paired with a multiplication operation in the next iteration of said one loop. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed.

    4.
    发明专利
    未知

    公开(公告)号:DE69614772T2

    公开(公告)日:2002-07-04

    申请号:DE69614772

    申请日:1996-06-10

    Applicant: IBM

    Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

    DATA STORAGE ARRAY
    5.
    发明专利

    公开(公告)号:CA2532766C

    公开(公告)日:2011-04-05

    申请号:CA2532766

    申请日:2004-07-07

    Applicant: IBM

    Abstract: A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.

    6.
    发明专利
    未知

    公开(公告)号:ES2160770T3

    公开(公告)日:2001-11-16

    申请号:ES96304352

    申请日:1996-06-10

    Applicant: IBM

    Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

    DATA STORAGE ARRAY
    7.
    发明专利

    公开(公告)号:CA2532766A1

    公开(公告)日:2005-01-20

    申请号:CA2532766

    申请日:2004-07-07

    Applicant: IBM

    Abstract: A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as Winograd code, a Reed Solomon code , an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasure s of the data storage units and the check storage units can be corrected by th e array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.

    8.
    发明专利
    未知

    公开(公告)号:AT205012T

    公开(公告)日:2001-09-15

    申请号:AT96304352

    申请日:1996-06-10

    Applicant: IBM

    Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

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