公开(公告)号：MY122998A

公开(公告)日：2006-05-31

申请号：MYPI20010041

申请日：2001-01-05

Applicant: IBM

Inventor： BRIAN MITCHELL BASS ,  MICHAEL STEVEN SIEGEL ,  ANTHONY MATTEO GALLO ,  MARCO C HEDDES ,  JEAN LOUIS CALVIGNAC ,  STEVEN KENNETH JENKINS ,  GORDON TAYLOR DAVIS ,  ROSS BOYD LEAVENS ,  FABRICE JEAN VEPLANKEN

IPC: G06F9/46 ,  H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60

Abstract: A SYSTEM AND METHOD OF FRAME PROTOCOL CLASSIFICATION AND PROCESSING IN A SYSTEM FOR DATA PROCESSING (E.G, SWITCHING OR ROUTING DATA PACKETS OR FRAME). THE PRESENT INVENTION INCLUDES ANALYZING A PORTION OF THE FRAME ACCORDING TO PREDERTERMINED TESTS, THE STORING KEY CHARACTERISTICS OF THE PACKET FOR USE IN SUNSEQUENT PROCESSING OF THE FRAME. THE KEY CHARACTERISTICS FOR THE FRAME (OR INPUT INFORMATION UNIT) INCLUDE THE TYPE OFLAYER 3 PROTOCOL USED IN THE FRAME, THE LAYER 2 ENCAPSULATION TECHNIQUE, THE STARTING INSTRUCTION ADDRESS, FLAGS INDICATING WETHER THE FRAME USES A VIRTUAL LOCAL AREA NETWORK, AND THE IDENTITY OF THE DATA FLOW TO WHICH THE FRAME BELONGS. MUCH OF THE ANALYSIS IS PREFERABLY DONE USING HARDWARE SO THAT IT CAN BE COMPLETED QUIKLY AND IN A UNIFORM TIME PERIOD. THE STORED CHARACTERISTICS OF THE FRAME ARE THEN USED BY THE NETWORK PROCESSING COMPLEX IN ITS PROCESSING OF THE FRAME. THE PROCESSOR (12, 110) IS PRECONDITIONED WITH A STARTING INSTRUCTION ADDRESS AND THE LOCATION OF THE BGINNING OF THE LAYER 3 HEADER AS WELL AS FLAGS FOR THE TYPE OF FRAME. THAT IS, THE INSTRUCTION ADDRESS OR CODE ENTRY POINT IS USED BY THE PROCESSOR (12, 110) TO START PROCESSING FOR A FRAME AT THE RIGHT PLACE, BASED ON THE TYPE OF FRAME. ADDITIONAL INSTRUCTION ADDRESSES CAN BE STACKED AND USED SEQUENTIALLY AT BRANCHES TO AVOID ADDITIONAL TESTS AND BRANCHING INSTRUCTIONS. ADDITIONALLY, FRAMES COMPRISING A DATA FLOW CAN BE PROCESSED AND FORWARDED IN THE SAME ORDER IN WHICH THERE ARE RECEIVED. FIGURE 4

公开(公告)号：MY127002A

公开(公告)日：2006-11-30

申请号：MYPI20005855

申请日：2000-12-13

Applicant: IBM

Inventor： BRIAN MITCHELL BASS ,  MICHAEL STEVEN SIEGEL ,  MARCO C HEDDES ,  JEAN LOUIS CALVIGNAC ,  STEVEN KENNETH JENKINS ,  MICHAEL RAYMOND TROMBLEY ,  FABRICE JEAN VERPLANKEN

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02 ,  G06F13/00 ,  G06F13/16 ,  G06F15/167 ,  G11C11/407 ,  H04L12/56

Abstract: THE ABILITY OF NETWORK PROCESSORS (50A, 50B, 50N) TO MOVE DATA TO AND FROM DYNAMIC RANDOM ACCESS MEMORY (DRAM) CHIPS (56, 58) USED COMPUTER SYSTEMS IS ENHANCED IN SEVERAL RESPECTS. IN ONE ASPECT OF THE INVENTION, TWO DOUBLE DATA RATE DRAMS ARE USED IN PARALLEL TO DOUBLE THE BANDWIDTH FOR INCREASED THROUGHPUT OF DATA. THE MOVEMENT OF DATA IS FURTHER IMPROVED BY SETTING 4 BANKS OF FULL 'READ' AND 4 BANKS OF FULL 'WRITE' BY THE NETWORK PROCESSOR FOR EVERY REPETITION OF THE DRAM TIME CLOCK. A SCHEME FOR RANDOMIZED 'READ' AND 'WRITE' ACCESS BY THE NETWORK PROCESSOR IS DISCLOSED. THIS SCHEME IS PARTICULARLY APPLICABLE TO NETWORKS SUCH AS ETHERNET THAT UTILIZE VARIABLE FRAME SIZES. (THE MOST ILLUSTRATIVE DRAWING IS FIGURE 2)

公开(公告)号：SG90222A1

公开(公告)日：2002-07-23

申请号：SG200007697

申请日：2000-12-28

Applicant: IBM

Inventor： BRIAN MITCHELL BASS ,  JEAN LOUIS CALVIGNAC ,  MARCO C HEDDES ,  STEVEN KENNETH JENKINS ,  MICHAEL STEVEN SIEGEL ,  MICHAEL RAYMOND TROMBLEY ,  FABRICE JEAN VERPLANKEN

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/00 ,  G06F13/16 ,  G06F15/167 ,  G11C11/407 ,  H04L12/56

Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full "read' and 4 banks of full "write' by the network processor for every repetition of the DRAM time clock. A scheme for randomized "read' and "write' access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.