公开(公告)号：EP2033213A4

公开(公告)日：2012-08-01

申请号：EP07757974

申请日：2007-03-06

Applicant: IBM

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  B05D3/00 ,  C23C16/34 ,  C23C16/505 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

公开(公告)号：JP2004221556A

公开(公告)日：2004-08-05

申请号：JP2003421709

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEE BYOUNG HUN ,  DIRAHOUI BACHIR ,  LEOBANDUNG EFFENDI ,  SU TAI-CHI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/518 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit that uses a process consolidation combining the substitution gate process using a three-layer hard mask consumed during the process and source/drain silicides.
SOLUTION: In the process, a first temporary gate sidewall spacer defines a rising source/drain formation area, a second temporary spacer defines a source/drain injection and source/drain silicification area, and the temporary gate is protected from being silicified by the hard mask.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种集成电路，其使用使用在处理期间消耗的三层硬掩模和源极/漏极硅化物的组合取代栅极工艺的处理固结。 解决方案：在该过程中，第一临时栅极侧壁间隔物限定上升的源极/漏极形成区域，第二临时间隔物限定源极/漏极注入和源极/漏极硅化区域，并且保护临时栅极不被硅化 用硬面罩。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：WO2007136907A2

公开(公告)日：2007-11-29

申请号：PCT/US2007063377

申请日：2007-03-06

Applicant: IBM ,  YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

Inventor： YANG DAEWON ,  LEE WOO-HYEONG ,  SU TAI-CHI ,  WANG YUN-YU

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/505 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8W/cm 2 and 5.0W/cm 2 ; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Abstract translation: 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。