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    RESIDUAL STATUS REPORTING DURING CHAINED CYCLE STEAL INPUT/ OUTPUT OPERATIONS
    1.
    发明专利
    RESIDUAL STATUS REPORTING DURING CHAINED CYCLE STEAL INPUT/ OUTPUT OPERATIONS 未知

    公开(公告)号：AU2475277A

    公开(公告)日：1978-11-09

    申请号：AU2475277

    申请日：1977-05-02

    Applicant: IBM

    Inventor： BOURKE DONALL GARRAID ,  VERGARI LOUIS PETER

    IPC: G06F13/10 ,  G06F13/34 ,  G06F3/00

    Abstract: A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

    DATA PROCESSING APPARATUS
    3.
    发明专利
    DATA PROCESSING APPARATUS 未知

    公开(公告)号：MY8500449A

    公开(公告)日：1985-12-31

    申请号：MY8500449

    申请日：1985-12-30

    Applicant: IBM

    Inventor： BOUKNECHT MAX ABBOT ,  VERGARI LOUIS PETER

    IPC: G06F13/40 ,  G06F13/36 ,  G06F13/00

    Abstract: In a data processing system which includes a base central processing unit, channel, and input/output (I/O) interface to which peripheral devices may be attached, a special attachment is disclosed. The attachment made to the base I/O interface includes connector circuitry which is required when the signals on the input/output interface must be repowered to peripheral devices in an expansion input/output unit, power isolation must be provided between a base data processing system and I/O expansion unit, or a remote peripheral device is to be attached to the base data processing system I/O interface. The connector circuit includes logic which responds to the normal I/O interface signals to energize drivers in the connector circuit to achieve repowering of signals on bidirectional signal lines and unidirectional signal lines.

    5.
    发明专利
    未知

    公开(公告)号：DE2719203A1

    公开(公告)日：1977-11-10

    申请号：DE2719203

    申请日：1977-04-29

    Applicant: IBM

    Inventor： BOURKE DONALL GARRAID ,  VERGARI LOUIS PETER

    IPC: G06F13/10 ,  G06F13/34 ,  G06F3/04 ,  G06F9/00

    Abstract: A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

    6.
    发明专利
    未知

    公开(公告)号：CH620778A5

    公开(公告)日：1980-12-15

    申请号：CH518677

    申请日：1977-04-26

    Applicant: IBM

    Inventor： BOUKNECHT MAX ABBOTT ,  BOURKE DONALL GARRAID ,  VERGARI LOUIS PETER

    IPC: G06F13/12 ,  G06F9/46 ,  G06F13/34 ,  G06F3/04

    Abstract: Improvements introduced in a peripheral device control unit with improved counting logic, for use in a data processing system including a central processing unit, a memory unit, a logic input-output control unit and a line general coupling (i/f). (Machine-translation by Google Translate, not legally binding)

    9.
    发明专利
    未知

    公开(公告)号：DE2758023A1

    公开(公告)日：1978-07-13

    申请号：DE2758023

    申请日：1977-12-24

    Applicant: IBM

    Inventor： BOUKNECHT MAX ABBOTT ,  VERGARI LOUIS PETER

    IPC: G06F13/36 ,  G06F13/40 ,  G06F3/04

    Abstract: In a data processing system which includes a base central processing unit, channel, and input/output (I/O) interface to which peripheral devices may be attached, a special attachment is disclosed. The attachment made to the base I/O interface includes connector circuitry which is required when the signals on the input/output interface must be repowered to peripheral devices in an expansion input/output unit, power isolation must be provided between a base data processing system and I/O expansion unit, or a remote peripheral device is to be attached to the base data processing system I/O interface. The connector circuit includes logic which responds to the normal I/O interface signals to energize drivers in the connector circuit to achieve repowering of signals on bidirectional signal lines and unidirectional signal lines.

    DATA PROCESSING APPARATUS
    10.
    发明专利
    DATA PROCESSING APPARATUS 未知

    公开(公告)号：HK48484A

    公开(公告)日：1984-06-15

    申请号：HK48484

    申请日：1984-06-07

    Applicant: IBM

    Inventor： BOUKNECHT MAX ABBOT ,  VERGARI LOUIS PETER

    IPC: G06F13/40 ,  G06F13/36 ,  G06F13/00

    Abstract: In a data processing system which includes a base central processing unit, channel, and input/output (I/O) interface to which peripheral devices may be attached, a special attachment is disclosed. The attachment made to the base I/O interface includes connector circuitry which is required when the signals on the input/output interface must be repowered to peripheral devices in an expansion input/output unit, power isolation must be provided between a base data processing system and I/O expansion unit, or a remote peripheral device is to be attached to the base data processing system I/O interface. The connector circuit includes logic which responds to the normal I/O interface signals to energize drivers in the connector circuit to achieve repowering of signals on bidirectional signal lines and unidirectional signal lines.

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