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12 records (took 0.017 seconds)

    1.
    发明专利
    未知

    公开(公告)号：CH619308A5

    公开(公告)日：1980-09-15

    申请号：CH518877

    申请日：1977-04-26

    Applicant: IBM

    Inventor： BOURKE DONALL GARRAID ,  VERGARI LOUIS PETER

    IPC: G06F13/10 ,  G06F13/34 ,  G06F9/46 ,  G06F3/00

    Abstract: A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

    TRANSLATOR LOOKAHEAD CONTROLS
    2.
    发明专利
    TRANSLATOR LOOKAHEAD CONTROLS 未知

    公开(公告)号：AU2474177A

    公开(公告)日：1978-11-09

    申请号：AU2474177

    申请日：1977-05-02

    Applicant: IBM

    Inventor： BOURKE DONALL GARRAID

    IPC: G06F12/02 ,  G06F13/06 ,  G06F9/20

    Abstract: Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory.

    4.
    发明专利
    未知

    公开(公告)号：DE2719203A1

    公开(公告)日：1977-11-10

    申请号：DE2719203

    申请日：1977-04-29

    Applicant: IBM

    Inventor： BOURKE DONALL GARRAID ,  VERGARI LOUIS PETER

    IPC: G06F13/10 ,  G06F13/34 ,  G06F3/04 ,  G06F9/00

    Abstract: A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

    6.
    发明专利
    未知

    公开(公告)号：CH620778A5

    公开(公告)日：1980-12-15

    申请号：CH518677

    申请日：1977-04-26

    Applicant: IBM

    Inventor： BOUKNECHT MAX ABBOTT ,  BOURKE DONALL GARRAID ,  VERGARI LOUIS PETER

    IPC: G06F13/12 ,  G06F9/46 ,  G06F13/34 ,  G06F3/04

    Abstract: Improvements introduced in a peripheral device control unit with improved counting logic, for use in a data processing system including a central processing unit, a memory unit, a logic input-output control unit and a line general coupling (i/f). (Machine-translation by Google Translate, not legally binding)

    OUTER AND ASYNCHRONOUS STORAGE EXTENSION SYSTEM
    7.
    发明专利
    OUTER AND ASYNCHRONOUS STORAGE EXTENSION SYSTEM 未知

    公开(公告)号：AU2475077A

    公开(公告)日：1978-11-09

    申请号：AU2475077

    申请日：1977-05-02

    Applicant: IBM

    Inventor： BOURKE DONALL GARRAID ,  PUTTLITZ FREDERIC JOHN

    IPC: G06F12/14 ,  G06F9/34 ,  G06F12/02 ,  G06F12/06 ,  G06F9/16 ,  G06F13/06

    Abstract: Extending the size of the main memory of a data processing system having a synchronous inner storage unit by attaching a relocation translator having special connection interfaces and translated addressing for attaching a synchronous outer storage unit and an asynchronous storage unit which may be remotely located from the processor. A differnt form of storage cycle is generated by the translator for interfacing each of the three storage units being accessed. The translator performs address translation which expands the number of bits in the physical address to support the extended main memory. The extended address uses a concatenation of a program-derived address and a machine-derived address key.

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