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公开(公告)号：DE2719295A1
公开(公告)日：1977-11-17
申请号：DE2719295
申请日：1977-04-29
Applicant: IBM
Inventor： DAVIS MICHAEL IAN , MAYES GARY WAYNE , MCDERMOTT THOMAS STEPHEN , WISE LARRY EDWARD
Abstract: A data processing system is described wherein, during linkage to a subroutine, by a single machine instruction, a complete status save and the assignment of a dynamic work area are effected. By another single machine instruction the process is reversed. The elements of the complete machine status and the dynamic work area are retained in a hardware controlled stack, thus permitting nesting of the subroutine calls.
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公开(公告)号：DE2716520A1
公开(公告)日：1977-11-10
申请号：DE2716520
申请日：1977-04-14
Applicant: IBM
Inventor： BIRNEY RICHARD EUGENE , DAVIS MICHAEL IAN , HOOD ROBERT ALLEN , GRAYBIEL LYNN ALLAN , BOCA RATON FLA , KAHN SAMUEL , OSBORNE WILLIAM STEESE , BOURKE DONALL GARRAID , PUTTLITZ FREDERIC JOHN
Abstract: The look ahead circuits are for an address relocation translator which contains stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. An additional pair of bit positions are provided with each SR to receive look ahead bits from decoder loading circuits which decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block. During each subsequent address translation the loaded look ahead bits are outgated while the block address is being read from an SR. The look ahead bits are decoded for selecting the required storage unit component of the main memory, and a translator interface is switched to that unit. The look ahead bits are handled by parallel high speed circuits so that the required storage unit is selected before a storage unit cycle is generated by the translator for accessing the addressed block.
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公开(公告)号：CH616013A5
公开(公告)日：1980-02-29
申请号：CH519877
申请日：1977-04-27
Applicant: IBM
Inventor： DAVIS MICHAEL IAN
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公开(公告)号：AU2474677A
公开(公告)日：1978-11-09
申请号：AU2474677
申请日：1977-05-02
Applicant: IBM
Inventor： BIRNEY RICHARD EUGENE , HOOD ROBERT ALLEN , DAVIS MICHAEL IAN
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公开(公告)号：DE2718051A1
公开(公告)日：1977-11-10
申请号：DE2718051
申请日：1977-04-22
Applicant: IBM
Inventor： DAVIS MICHAEL IAN
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Patent Agency Ranking
公开(公告)号：DE3475446D1
公开(公告)日：1989-01-05
申请号：DE3475446
申请日：1984-06-25
Applicant: IBM
Abstract: A terminal includes a raster-scan display device and a refresh buffer having bit planes (1-6) each with a respective bit storage location corresp. to each addressable pel position on the display screen. The bit planes are addressed in coordination with the line-by-line scanning of the display device to provide multi-bit per pel output data defining the colour and/or intensity of each pel on the screen. In order to store alphanumeric data on such a terminal, high resolution luminance data, defining alphanumeric characters each as a selection of 'on' bits within a respective character box, is stored in a bit plane (luminance plane 1). At least one further bit plane (attribute plane 2) is used to store low resolution colour data which defines at least the colour and/or intensity of the foreground and background of the characters.
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公开(公告)号：DE3164650D1
公开(公告)日：1984-08-16
申请号：DE3164650
申请日：1981-03-10
Applicant: IBM
Inventor： DAVIS MICHAEL IAN , SZE DANIEL TSI WING
IPC: H04L5/22 , G06F13/00 , G06F15/173 , G06F15/16
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公开(公告)号：AU2474877A
公开(公告)日：1978-11-09
申请号：AU2474877
申请日：1977-05-02
Applicant: IBM
Inventor： BIRNEY RICHARD EUGENE , DAVIS MICHAEL IAN
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公开(公告)号：AU2474077A
公开(公告)日：1978-11-09
申请号：AU2474077
申请日：1977-05-02
Applicant: IBM
Inventor： DAVIS MICHAEL IAN
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公开(公告)号：AU4746472A
公开(公告)日：1974-04-11
申请号：AU4746472
申请日：1972-10-05
Applicant: IBM
Inventor： DAVIS MICHAEL IAN , LOFFREDO JOHN MARIO , RICKARD PATRICK LEE , WISE LARRY EDWARD
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