公开(公告)号：JP2000243938A

公开(公告)日：2000-09-08

申请号：JP2000035483

申请日：2000-02-14

Applicant: IBM

Inventor： LAM CHUNG H ,  MILES GLEN L ,  NAKOS JAMES S ,  WILLETS CHRISTA R

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To reduce the size of an NVRAM cell by allowing a cell selection circuit for selecting a cell in an array to respond to a plurality of logic gates and the logic gates to receive data being selected from the array. SOLUTION: A word line 180 is capacitively coupled to floating gates 180f and 228, and at the same time a word line 182 is capacitively coupled to floating gates 182f and 230. Then, four cells indicated by the floating gates 182f and floating gate parts 180f, 228, and 230 are allowed to share each of bit line diffusion regions 224 and 234, and a plurality of logic gates in a selection circuit for selecting the cells receive the data of a selected cell, thus reducing the size of an NVRAM cell for including in a single integrated circuit chip.